TC62D748AFG Datasheet, PDF (8/19 Pages) Toshiba Semiconductor – 16-Output Constant Current LED Driver

TC62D748AFG/AFNAG/BFNAG
Switching Characteristics (Unless otherwise specified, V_DD = 3.3V, T_a = 25°C)
Characteristics
Symbol
Test
Circuits
Test Conditions
Min Typ. Max Unit
SCK- OUT0
SLAT - OUT0
OE - OUT0
Propagation delay ^SCK-SOUT
t
i
m
e _{SCK- OUT0}
SLAT - OUT0
OE - OUT0
SCK-SOUT
Output rise time
Output fall time
Enable pulse width
Clock pulse width
Latch pulse width
t_pLH1
t_pLH2
t_pLH3
t_pLH
t_pHL1
t_pHL2
t_pHL3
t_pHL
t_or
t_of
t_wOE(L)
t_wOE(H)
t_wSCK
t_wSLAT
6
SLAT = “H”, OE = “L”
⎯
50
65
ns
6
OE = “L”
⎯
50
65
ns
6
SLAT = “H”
⎯
50
65
ns
6
C_L=10.5 pF
6
SLAT = “H”, OE = “L”
10
20
35
ns
⎯
30
40
ns
6
OE = “L”
⎯
30
40
ns
6
SLAT = “H”
⎯
30
40
ns
6
C_L=10.5 pF
10
20
35
ns
6
10 to 90% of voltage waveform ⎯
30
45
ns
6
90 to 10% of voltage waveform ⎯
10
20
ns
6
OE = “L”
6
OE = “H”
25
⎯
⎯
ns
50
⎯
⎯
6
SCK = “H” or “L”
6
SLAT = “H”
20
⎯
⎯
ns
20
⎯
⎯
ns
Switching Characteristics (Unless otherwise specified, V_DD = 5.0V, T_a = 25°C)
Characteristics
Symbol
Test
Circuits
Test Conditions
Min Typ. Max Unit
SCK- OUT0
SLAT - OUT0
OE - OUT0
Propagation delay ^SCK-SOUT
t
i
m
e _{SCK- OUT0}
SLAT - OUT0
OE - OUT0
SCK-SOUT
Output rise time
Output fall time
Enable pulse width
Clock pulse width
Latch pulse width
t_pLH1
t_pLH2
t_pLH3
t_pLH
t_pHL1
t_pHL2
t_pHL3
t_pHL
t_or
t_of
t_wOE(L)
t_wOE(H)
t_wSCK
t_wSLAT
6
SLAT = “H”, OE = “L”
⎯
50
65
ns
6
OE = “L”
⎯
50
65
ns
6
SLAT = “H”
⎯
50
65
ns
6
C_L=10.5 pF
10
20
35
ns
6
SLAT = “H”, OE = “L”
⎯
30
40
ns
6
OE = “L”
⎯
30
40
ns
6
SLAT = “H”
⎯
30
40
ns
6
C_L=10.5 pF
10
20
35
ns
6
10 to 90% of voltage waveform ⎯
30
45
ns
6
90 to 10% of voltage waveform ⎯
10
20
ns
6
OE = “L”
6
OE = “H”
25
⎯
⎯
ns
50
⎯
⎯
6
SCK = “H” or “L”
6
SLAT = “H”
20
⎯
⎯
ns
20
⎯
⎯
ns
8
2010-03-05