TMP88PH40NG Datasheet, PDF (77/158 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP88PH40NG
• A sampling delay is provided for use in modes where sampling is made while PWM is on or the lower
phases are conducting current. It helps to prevent erroneous detection due to noise that occurs immedi-
ately after the transistor turns on, by starting sampling a set time after the PWM signal turned on.
• When detecting position while PWM is on or the lower phases are conducting current, a method can be
selected whether to recount occurrences of matched position detection after being compared for each
PWM signal on (logical sum of three-phase PWM signals) (e.g., starting from 0 in each PWM cycle) or
counting occurrences of matching continuously ( PDCRB<SPLMD> is used to enable/disable recount-
ing occurrences of matching while PWM is on).
11.3.2 Position Detection Circuit Register Functions
PDCRC
5, 4
3
2 to 0
PDCRB
7, 6
5, 4
3 to 0
PDCRA
7
6
5
4
3
2
1
0
EMEM
SMON
PDTCT
Hold result of position detec-
tion at PWM edge
(Detect position detected
position)
These bits hold the comparison result of position detection at falling or rising edge of
PWM pulse. Bits 5 and 4 are set to 1 when position is detected at the falling or the rising
edge, respectively. They show whether position is detected in the current PWM pulse,
during PWM off, or in the immediately preceding PWM pulse.
Monitor sampling status
When read, this bit shows the sampling status.
Hold position signal input sta- This bit holds the status of the position signal input at the time position detection started in
tus
unmatch mode.
SPLCK
Sampling period
SPLMD
Sampling mode
PDCMP
Sampling count
Select fc/2², fc/2³, fc/2⁴, or fc/2⁵ for the position detection sampling period.
Select one of three modes: sampling only when PWM signal is active (when PWM is on),
sampling regularly, or sampling when the lower side (X, Y, Z) phases are conducting cur-
rent.
In ordinary mode, when the port status and the set expected value match and continu-
ously match as many times as the sampling counts set, a position detection signal is out-
put and an interrupt is generated. In unmatch detection mode, when the said status and
value do not match and continuously unmatch as many times as the sampling counts set,
a position detection signal is output and an interrupt is generated.
SWSTP
SWSTT
SPTM3
STTM2
PDNUM
RCEN
DTMD
PDCEN
Stop sampling in software
Start sampling in software
Stop sampling using Timer 3
Start sampling using Timer 2
Number of position signal
input pins
Recount occurrences of
matching when PWM is on
Position detection mode
Position detection function
Sampling can be stopped in software by setting this bit to 1 (e.g., by writing to this regis-
ter).
Sampling is performed before stopping and when position detection results match, a posi-
tion detection interrupt is generated, with sampling thereby stopped.
Sampling can be started by setting this bit to 1 (e.g., by writing to this register).
Sampling can be stopped by a trigger from Timer 3 by setting this bit to 1.
Sampling is performed before stopping and when position detection results match, a posi-
tion detection interrupt is generated, with sampling thereby stopped.
Sampling can be started by a trigger from Timer 3 by setting this bit to 1.
Select whether to use three pins (PDU/PDV/PDW) or one pin (PDU only) for position sig-
nal input. When one pin is selected, the expected values of PDV and PDW are ignored.
When performing position detection with two pins or a pin other than PDU, position signal
input can be masked as 0 by setting unused pin(s) for output.
When performing sampling while PWM is on, occurrences of matching are recounted
each time PWM signal turns on by setting this bit to 1 (when recounting occurrences of
matching, the count is reset each time PWM turns off). When this bit is set to 0, occur-
rences of matching are counted continuously regardless PWM interval.
Setting this bit to 0 selects ordinary mode where position is detected when the expected
value set in the register and the port input unmatch and then match.
Setting this bit to 1 selects unmatch detection mode where position is detected at the time
the port status changes to another one from the status in which it was when sampling
started.
The position detection function is activated by setting this bit to 1.
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