TCV7100AF Datasheet, PDF (7/17 Pages) Toshiba Semiconductor – Buck DC-DC Converter IC

TCV7100AF
Output Filter Capacitor Selection
Use a low-ESR electrolytic or ceramic capacitor as the output filter capacitor. Since a capacitor is generally
sensitive to temperature, choose one with excellent temperature characteristics. As a rule of thumb, its
capacitance should be 30 μF or greater for applications where V_OUT ≥ 2 V, and 60 μF or greater for applications
where V_OUT < 2 V. The capacitance should be set to an optimal value that meets the system’s ripple voltage
requirement and transient load response characteristics. The phase margin tends to decrease as the output
voltage is getting low. Enlarge a capacitance for output flatness when phase margin is insufficient, or the
transient load response characteristics cannot be satisfied. Since the ceramic capacitor has a very low ESR value,
it helps reduce the output ripple voltage; however, because the ceramic capacitor provides less phase margin, it
should be thoroughly evaluated.
Output filter capacitors with a smaller value mentioned above can be used by adding a phase compensation
circuit to the V_FB pin. For example, suppose using two 10μF ceramic capacitors as output filter capacitors; then
the phase compensation circuit should be programmed as follows:
C_P1 (μF) = 2 / R_FB1 (Ω) ··············· (3)
C_P2 (μF) = C_P1 (μF) × 10 ············· (4)
R_FB2 // R_P = R_{FB1 / 2 ·····················} (5)
* Set the upper cut-off frequency of C_P1 and R_FB1 to
approx. 80 kHz (f_OSC/10). ····················· (3)
* Choose the value of C_P2 to produce zero-frequency at
1/10th the upper cut-off frequency. ········· (4)
* If R_FB2 is less than half of R_FB1, R_P and C_P2 are not
necessary.··········································· (5)
(Only C_P1 allows programming of V_OUT above
1.8 V.)
L_X
V_OUT
V_FB
Figure 4 Phase Compensation Circuit
Examples of Component Values in the Phase Compensation Circuit (For Reference Only)
The following values need tuning, depending on the TCV7100AF’s I/O conditions and the board layout.
V_OUT
1.2 V
1.51 V
1.8 V
2.5 V
3.3 V
C_OUT
10 μF × 2
10 μF × 2
10 μF × 2
10 μF × 2
10 μF × 2
R_FB1
7.5 kΩ
16 kΩ
15 kΩ
5.1 kΩ
7.5 kΩ
R_FB2
15 kΩ
18 kΩ
12 kΩ
2.4 kΩ
2.4 kΩ
R_P
4.7 kΩ
15 kΩ
⎯
⎯
⎯
C_P1
270 pF
120 pF
180 pF
390 pF
270 pF
C_P2
2700 pF
1200 pF
⎯
⎯
⎯
The phase compensation circuit shown above delivers good transient load response characteristics with
small-value output filter capacitors by programming f₀ (the frequency at which the open-loop gain is equal to
0dB) to a high frequency. For output filter capacitors, use low-ESR ceramic capacitors with excellent temperature
characteristics (such as the JIS B characteristic). Although the external phase compensation circuit improves
noise immunity, they should be thoroughly evaluated to ensure that the system’s ripple voltage requirement and
transient load response characteristics are met.
Soft-Start Feature
The TCV7100AF has a soft-start feature.
If the SS pin is left open, the soft-start time, t_SS, for V_OUT defaults to 1 ms (typ.) internally.
The soft-start time can be extended by adding an external capacitor (C_SS) between the SS and SGND pins. The
soft-start time can be calculated as follows:
t_SS2 = 0.1⋅ C_SS ··························· (6)
t_SS2: Soft-start time (in seconds) when an external capacitor is
connected between SS and SGND.
C_SS: Capacitor value (μF)
The soft-start feature is activated when the TCV7100AF exits the undervoltage lockout (UVLO) state after
power-up and when the voltage at the EN pin has changed from logic low to logic high.
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2010-12-16