TMP86CH29BFG Datasheet, PDF (69/196 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP86CH29BFG
5.4 Port P5 (P57 to P50)
Port P5 is an 8-bit input/output port which is also used as a segment pins of LCD.
When used as input port, the respective output latch (P5DR) should be set to “1”.
During reset, the P5DR is initialized to “1”.
When used as a segment pins of LCD, the respective bit of P5LCR should be set to “1”. When used as an output
port, the respective P5LCR bit should be set to “0”.
P5 port output latch (P5DR) and P5 port terminal input (P5PRD) are located on their respective address.
When read the output latch data, the P5DR should be read and when read the terminal input data, the P5PRD reg-
ister should be read. If the terminal input data which is configured as LCD segment output is read, unstable data is
read.
OUSTTOENP
P5LCRi
P5LCRi input
Data input (P5PRD)
Data input (P5DR)
Data output (P5DR)
LCD data output
DQ
DQ
Output latch
P5i
Note:
i
=
7
to
0
Figure 5-5 Port P5
Port P5 control register
P5DR
(0005H)
R/W
7
P57
SEG16
6
P56
SEG17
5
P55
SEG18
4
P54
SEG19
3
P53
SEG20
2
P52
SEG21
1
P51
SEG22
0
P50
SEG23
(Initial value: 1111 1111)
P5LCR
7
6
5
4
3
2
1
0
(002AH)
(Initial value: 0000 0000)
Port P5/segment output control 0: P5 input/output port
P5LCR
R/W
(Set for each bit individually) 1: LCD segment output
P5PRD
7
6
5
4
3
2
1
0
(000BH)
P57
P56
P55
P54
P53
P52
P51
P50
Read only
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