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TMP86CH12MG Datasheet, PDF (69/182 Pages) Toshiba Semiconductor – 8 Bit Microcontroller | |||
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TMP86CH12MG
Watchdog Timer Control Register 1
WDTCR1
7
(0034H)
6
5
4
3
(ATAS) (ATOUT) WDTEN
2
1
WDTT
0
WDTOUT (Initial value: **11 1001)
WDTEN Watchdog timer enable/disable
WDTT
Watchdog timer detection time
[s]
WDTOUT Watchdog timer output select
0: Disable (Writing the disable code to WDTCR2 is required.)
1: Enable
NORMAL1/2 mode
DV7CK = 0
DV7CK = 1
SLOW1/2
mode
00
225/fc
217/fs
217/fs
01
223/fc
215/fs
215fs
10
221fc
213/fs
213fs
11
219/fc
211/fs
211/fs
0: Interrupt request
1: Reset request
Write
only
Write
only
Write
only
Note 1: After clearing WDTOUT to â0â, the program cannot set it to â1â.
Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Donât care
Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a
donât care is read.
Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode.
After clearing the counter, clear the counter again immediately after the STOP mode is inactivated.
Note 5: To clear WDTEN, set the register in accordance with the procedures shown in â1.2.3 Watchdog Timer Disableâ.
Watchdog Timer Control Register 2
WDTCR2
7
6
5
4
3
2
1
0
(0035H)
(Initial value: **** ****)
WDTCR2
Write
Watchdog timer control code
4EH: Clear the watchdog timer binary counter (Clear code)
B1H: Disable the watchdog timer (Disable code)
D2H: Enable assigning address trap area
Others: Invalid
Note 1: The disable code is valid only when WDTCR1<WDTEN> = 0.
Note 2: *: Donât care
Note 3: The binary counter of the watchdog timer must not be cleared by the interrupt task.
Note 4: Write the clear code 4EH using a cycle shorter than 3/4 of the time set in WDTCR1<WDTT>.
Write
only
6.2.2 Watchdog Timer Enable
Setting WDTCR1<WDTEN> to â1â enables the watchdog timer. Since WDTCR1<WDTEN> is initialized
to â1â during reset, the watchdog timer is enabled automatically after the reset release.
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