TMP86CH09NG Datasheet, PDF (67/154 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP86CH09NG
7. Watchdog Timer (WDT)
The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu-
rious noises or the deadlock conditions, and return the CPU to a system recovery routine.
The watchdog timer signal for detecting malfunctions can be programmed only once as “reset request” or “inter-
rupt request”. Upon the reset release, this signal is initialized to “reset request”.
When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter-
rupt.
Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to
effect of disturbing noise.
7.1 Watchdog Timer Configuration
fc/2²³ or fs/2¹⁵
fc/2²¹ or fs/2¹³
fc/2¹⁹ or fs/2¹¹
fc/2¹⁷ or fs/2⁹
Binary counters
Clock
Overflow
Clear ^{1 2}
2
Internal reset
Q
SR
Reset release
WDT output
R
SQ
Reset
request
Interrupt request
INTWDT
interrupt
request
WDTEN
WDTT
Writing
Writing
disable code clear code
Controller
WDTOUT
0034_H
WDTCR1
0035_H
WDTCR2
Watchdog timer control registers
Figure 7-1 Watchdog Timer Configuration
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