TCA62746AFG Datasheet, PDF (6/25 Pages) Toshiba Semiconductor – 16-Output Constant Current LED Driver with Output Open/Short Detection

TCA62746AFG/AFNG
Absolute Maximum Ratings (T_a = 25°C)
Characteristics
Symbol
Rating *1
Unit
P o w e r s u p p l y v o l t a g e V_DD
−0.4 to 6.0
V
Output current
I_O
55
mA
L o g i c i n p u t v o l t a g e V_IN
−0.3 to V_DD + 0.3 *2
V
O u t p u t v o l t a g e V_O
−0.3 to 17
V
O p e r a t i n g t e m p e r a t u r e T_opr
−40 to 85
°C
S t o r a g e t e m p e r a t u r e T_stg
−55 to 150
°C
T h e r m a l r e s i s t a n c e R_th(j-a)
94(AFG type When mounted PCB)/120(AFNG type When mounted PCB) *3
P o w e r d i s s i p a t i o n P_D 1.32(AFG type When mounted PCB)/1.04(AFNG type When mounted PCB) *3,4
Note1: Voltage is ground referenced.
Note2: However, do not exceed 6V.
Note3: PCB condition 76.2 x 114.3 x 1.6 mm, Cu 30% (SEMI conforming)
Note4: The power dissipation decreases the reciprocal of the saturated thermal resistance (1/ Rth(j-a)) for each
degree (1°C) that the ambient temperature is exceeded (Ta = 25°C).
Recommended Operating Conditions
°C/W
W
DC Items (Unless otherwise specified, T_a = −40°C to 85°C)
Characteristics
Symbol
Test Conditions
Min Typ. Max Unit
P o w e r s u p p l y v o l t a g e V_DD
⎯
4.5
⎯
O u t p u t v o l ta ge wh e n O F F V_{O (OFF)} OUTn
⎯
⎯
O u t p u t v o l t a g e w h e n O N V_{O (ON)} OUTn
0.7
⎯
High level logic input voltage V_IH
⎯
2.0
⎯
Low level logic input voltage V_IL
⎯
GND ⎯
High level SOUT output current I_OH V_DD = 5 V
⎯
⎯
Low level SOUT output current I_OL V_DD = 5 V
⎯
⎯
Constant current output
I_O
OUTn
2
⎯
AC Items (Unless otherwise specified, V_DD = 4.5 to 5.5 V, T_a = −40°C to 85°C)
5.5
V
16
V
4
V
V_DD
V
0.8
V
−1 mA
1
mA
50 mA
Characteristics
Symbol Test Circuits
Test Conditions
Min Typ. Max Unit
Serial data transfer frequency f_SCK
7
⎯
⎯
⎯
25 MHz
C l o c k p u l s e w i d t h t_wSCK
7
SCK = “H” or “L”
20
⎯
⎯
ns
L a t c h p u l s e w i d t h t_wSLAT
7
SLAT = “H”
20
⎯
⎯
ns
Enable pulse width
t_wOE1
t_wOE2
7
OE = “H” or “L” ,R_EXT = 500 Ω
⎯
When error is detected *1
100 ⎯
⎯
ns
2
⎯
⎯
µs
t_HOLD1
7
⎯
5
⎯
⎯
ns
t_HOLD2
7
Hold
time
t_HOLD3
7
⎯
5
⎯
⎯
ns
⎯
10
⎯
⎯
ns
t_HOLD4
7
⎯
10
⎯
⎯
ns
t_SETUP1
7
⎯
5
⎯
⎯
ns
t_SETUP2
7
Setup time
t_SETUP3
7
⎯
5
⎯
⎯
ns
⎯
10
⎯
⎯
ns
t_SETUP4
7
⎯
10
⎯
⎯
ns
Maximum clock rise time
t_r
7
*2
⎯
⎯ 500 ns
Maximum clock fall time
t_f
7
*2
⎯
⎯ 500 ns
Note1: Please refer to page 16 for details of the error detection.
Note2: If the device is connected in a cascade and the tr/tf of the clock waveform increases due to deceleration of the clock waveform,
it may not be possible to achieve the timing required for data transfer. Please keep these timing conditions in mind when
designing your application.
6
2007-05-22