TMP88CH40NG Datasheet, PDF (53/148 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP88CH40NG
Example :Setting watchdog timer interrupt
LD
SP, 02BFH
LD
(WDTCR1), 00001000B
: Sets the stack pointer
: WDTOUT ← 0
6.2.5 Watchdog Timer Reset
When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset
request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset
time is maximum 24/fc [s] ( max. 1.2 µs @ fc = 20 MHz).
Clock
2¹⁷/fc
2¹⁹/fc [s]
Binary counter
1
2
30
1
2
3
Overflow
INTWDT interrupt request
(WDTCR1<WDTOUT>= "0")
Internal reset
(WDTCR1<WDTOUT>= "1")
Write 4E_H to WDTCR2
Figure 6-2 Watchdog timer Interrupt and Reset
(WDTT=11B)
0
A reset occurs
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