TC74VHC164F_07 Datasheet, PDF (5/11 Pages) Toshiba Semiconductor – 8-Bit Shift Register (S-IN, P-OUT)

Timing Requirements (input: t_r = t_f = 3 ns)
Characteristics
Symbol
Minimum pulse width
(CK)
Minimum pulse width
( CLR )
Minimum set-up time
t_{w (L)}
t_{w (H)}
t_{w (L)}
t_s
Minimum hold time
t_h
Minimum removal time
t_rem
( CLR )
TC74VHC164F/FN/FT/FK
Test Condition
―
―
―
―
―
Ta = 25°C
Ta =
−40 to
85°C ^Unit
V_CC (V) Typ. Limit Limit
3.3 ± 0.3 ―
5.0 5.0
ns
5.0 ± 0.5 ―
5.0 5.0
3.3 ± 0.3 ―
5.0 5.0
ns
5.0 ± 0.5 ―
5.0 5.0
3.3 ± 0.3 ―
5.0 6.0
ns
5.0 ± 0.5 ―
4.5 4.5
3.3 ± 0.3 ―
0.0 0.0
ns
5.0 ± 0.5 ―
1.0 1.0
3.3 ± 0.3 ―
2.5 2.5
ns
5.0 ± 0.5 ―
2.5 2.5
AC Characteristics (input: t_r = t_f = 3 ns)
Characteristics
Symbol
Propagation delay
time
t_pLH
(CK-Q)
t_pHL
Propagation delay
time
t_pHL
( CLR -Q)
Maximum clock
frequency
f_max
Input capacitance
C_IN
Power dissipation
capacitance
C_PD
Test Condition
V_CC (V) C_L (pF)
15
3.3 ± 0.3
50
―
15
5.0 ± 0.5
50
15
3.3 ± 0.3
50
―
15
5.0 ± 0.5
50
15
3.3 ± 0.3
50
―
15
5.0 ± 0.5
50
―
Ta = 25°C
Min Typ. Max
―
8.4 12.8
― 10.9 16.3
―
5.8 9.0
―
7.3 11.0
―
8.3 12.8
― 10.8 16.3
―
5.2 8.6
―
6.7 10.6
80 125 ―
50
75
―
125 175 ―
85 115 ―
―
4
10
(Note) ―
76
―
Ta = −40 to
85°C
Min Max
1.0 15.0
1.0 18.5
1.0 10.5
1.0 12.5
1.0 15.0
1.0 18.5
1.0 10.0
1.0 12.0
65
―
45
―
105
―
75
―
―
10
―
―
Unit
ns
ns
MHz
pF
pF
Note: C_PD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I_{CC (opr)} = C_PD·V_CC·f_IN + I_CC
Noise Characteristics (input: t_r = t_f = 3 ns)
Characteristics
Symbol
Test Condition
Quiet output maximum dynamic V_OL
Quiet output minimum dynamic V_OL
Minimum high level dynamic input voltage
Maximum low level dynamic input voltage
V_OLP
V_OLV
V_IHD
V_ILD
C_L = 50 pF
C_L = 50 pF
C_L = 50 pF
C_L = 50 pF
Ta = 25°C
Unit
V_CC (V) Typ. Max
5.0
0.5 0.8
V
5.0
−0.5 −0.8
V
5.0
―
3.5
V
5.0
―
1.5
V
5
2007-10-01