TC74HC193AP_07 Datasheet, PDF (5/12 Pages) Toshiba Semiconductor – Synchronous Up/Down Binary Counter

Timing Requirements (input: t_r = t_f = 6 ns)
Characteristics
Symbol
Minimum pulse width
(CK)
Minimum pulse width
( LOAD )
Minimum hold time
(CLR)
Minimum set-up time
(DATA- LOAD )
Minimum hold time
(DATA- LOAD )
Minimum removal time
( LOAD )
Minimum removal time
(CLR)
t_{W (H)}
t_{W (L)}
t_{W (L)}
t_{W (H)}
t_s
t_h
t_rem
t_rem
Clock frequency
f
TC74HC193AP/AF/AFN
Test Condition
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
V_CC (V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Ta = 25°C
Typ. Limit
⎯ 100
⎯
20
⎯
17
⎯
75
⎯
15
⎯
13
⎯ 100
⎯
20
⎯
17
⎯
75
⎯
15
⎯
13
⎯
0
⎯
0
⎯
0
⎯
50
⎯
10
⎯
9
⎯
50
⎯
10
⎯
9
⎯
5
⎯
25
⎯
29
Ta =
−40
~85°C
Limit
125
25
21
95
19
16
125
25
21
95
19
16
0
0
0
65
13
10
65
13
10
4
20
24
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
5
2007-10-01