TMP89FH46 Datasheet, PDF (45/390 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP89FH46
Table 2-4 Oscillation Start Operation at Release of the STOP Mode
Operation mode before the STOP
mode is started
Single-clock
mode
NORMAL1
NORMAL2
Dual-clock mode
SLOW1
High-frequency
clock
High-frequency
clock oscillation
circuit
High-frequency
clock oscillation
circuit
-
Low-frequency
clock
Oscillation start operation after release
The high-frequency clock oscillation circuit starts
oscillation.
-
The low-frequency clock oscillation circuit stops
oscillation.
Low-frequency
clock oscillation cir-
cuit
The high-frequency clock oscillation circuit starts
oscillation.
The low-frequency clock oscillation circuit starts
oscillation.
Low-frequency
clock oscillation cir-
cuit
The high-frequency clock oscillation circuit stops
oscillation.
The low-frequency clock oscillation circuit starts
oscillation.
Note: When the operation returns to the NORMAL2 mode, fc is input to the frequency division circuit of the warm-up counter.
2.3.6.2 IDLE1/2 and SLEEP1 modes
The IDLE1/2 and SLEEP1 modes are controlled by the system control register 2 (SYSCR2) and
maskable interrupts. The following states are maintained during these modes.
1. The CPU and the watchdog timer stop their operations. The peripheral circuits continue to oper-
ate.
2. The data memory, the registers, the program status word and the port output latches are all held
in the status in effect before IDLE1/2 or SLEEP1 mode was started.
3. The program counter holds the address of the instruction 2 ahead of the instruction which starts
the IDLE1/2 or SLEEP1 mode.
RA001
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