TMP91FY42FG Datasheet, PDF (42/332 Pages) Toshiba Semiconductor – Original CMOS 16-Bit Microcontroller

TMP91FY42
3.4.3
Interrupt Controller Operation
The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the
diagram shows the interrupt controller circuit. The right-hand side shows the CPU
interrupt request signal circuit and the halt release circuit.
For each of the 45 interrupt channels there is an interrupt request flag (Consisting of a
flip-flop), an interrupt priority setting register and a micro DMA start vector register. The
interrupt request flag latches interrupt requests from the peripherals. The flag is cleared
to zero in the following cases:
• when reset occurs
• when the CPU reads the channel vector after accepted its interrupt
• when executing an instruction that clears the interrupt (Write DMA start vector to
INTCLR register)
• when the CPU receives a micro DMA request (when micro DMA is set)
• when the micro DMA burst transfer is terminated
An interrupt priority can be set independently for each interrupt source by writing the
priority to the interrupt priority setting register (e.g., INTE0AD or INTE12). 6 interrupt
priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7)
disables interrupt requests from that source. The priority of non-maskable interrupts
(NMI pin interrupts and watchdog timer interrupts) is fixed at 7. If interrupt request with
the same level are generated at the same time, the default priority (The interrupt with
the lowest priority or, in other words, the interrupt with the lowest vector value) is used
to determine which interrupt request is accepted first.
The 3rd and 7th bits of the interrupt priority setting register indicate the state of the
interrupt request flag and thus whether an interrupt request for a given channel has
occurred.
The interrupt controller sends the interrupt request with the highest priority among
the simulateous interrupts and its vector address to the CPU. The CPU compares the
priority value <IFF2:0> in the status register by the interrupt request signal with the
priority value set;if the latter is higher, the interrupt is accepted. Then the CPU sets a
value higher than the priority value by 1 (+1) in the CPU SR<IFF2:0>. Interrupt request
where the priority value equals or is higher than the set value are accepted
simultaneously during the previous interrupt routine.
When interrupt processing is completed (after execution of the RETI instruction), the
CPU restores the priority value saved in the stack before the interrupt was generated to
the CPU SR<IFF2:0>.
The interrupt controller also has registers (4 channels) used to store the micro DMA
start vector. Writing the start vector of the interrupt source for the micro DMA processing
(See Table 3.4.1), enables the corresponding interrupt to be processed by micro DMA
processing. The values must be set in the micro DMA parameter register (e.g., DMAS and
DMAD) prior to the micro DMA processing.
91FY42-40
2006-11-08