TC9325F Datasheet, PDF (40/101 Pages) Toshiba Semiconductor – Single-Chip DTS Microcontroller (DTS-20)

TC9325F
2. Timer-Counter Function
The timer-counter consists of an 8-bit binary counter, a counter match register, a digital comparator, and
the control circuits to run these.
The timer-counter inputs a timer clock to an 8-bit binary counter. When the count of the 8-bit binary
counter matches the contents of the counter match register, the timer-counter outputs a match signal pulse
and generates an interrupt request. The timer-counter can be reset by the match pulse or by software. The
reset by match pulse can be enabled or disabled. INTR1/2 input, an instruction cycle, or a frequency of 1
kHz can be selected as a timer clock.
(1) Timer-counter register structure
The timer-counter registers consist of the counter data, a match register, and a control register.
φL15P2
Y1 Y2 Y4 Y8
ID0 ID1 ID2 ID3
φL16P2
Y1 Y2 Y4 Y8
ID4 ID5 ID6 ID7
φK15P2
Y1 Y2
Timer-counter match data
φK16P2
Y4 Y8
Y1 Y2
Outputs a match pulse at a match with the timer-counter
Y4 Y8
CT0 CT1 CT2 CT3
CT4 CT5 CT6 CT7
Timer-counter data
Y1 Y2 Y4 Y8
φL17P2 CK0 CK1 GT CR
The timer-counter data are read in binary to the data memory
as-are.
Timer clock selection
Timer-counter reset
Resets counter whenever 1 is set.
0: Enabled
Enables counter reset by match pulse _{1: Disabled}
CK0 CK1 CPU clock
Timer clock
0
0
0
1
1
0
1
1
*
4.5 MHz
75 kHz
*
*
INTR1 pin input
Instruction
cycle clock
562.5 kHz
25 kHz
25 kHz
1 kHz
The clock edge can be selected by the POL bit
0: Counts on rising edge.
1: Counts on falling edge.
Note: When using the timer-counter, the IE bit must be set to 1.
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2002-05-14