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TC4040BP_07 Datasheet, PDF (4/9 Pages) Toshiba Semiconductor – 12 Stage Ripple-Carry Binary Counter/Dividers | |||
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TC4040BP/BF/BFN
Dynamic Electrical Characteristics (Ta = 25°C, VSS = 0 V, CL = 50 pF)
Characteristics
Output transition time
(low to high)
Output transition time
(high to low)
Propagation delay time
( CLOCK -Q1)
Propagation delay time
( CLOCK -Q1)
Propagation delay time
( CLOCK -Q12)
Propagation delay time
( CLOCK -Q12)
Propagation delay time
(RESET-Q)
Max clock frequency
Min clock pulse width
Min pulse width
(RESET)
Min removal time
(RESET- CLOCK )
Max clock input rise time
Max clock input fall time
Input capacitance
Symbol
tTLH
tTHL
tpLH
tpHL
tpLH
tpHL
tpHL
fCL
tW
tW
trem
trCL
tfCL
CIN
Test Condition
â¯
â¯
â¯
â¯
â¯
â¯
â¯
â¯
â¯
â¯
â¯
â¯
â¯
VDD (V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Min Typ. Max
â¯
70 200
â¯
35 100
â¯
30
80
â¯
70 200
â¯
35 100
â¯
30
80
⯠160 360
â¯
80 160
â¯
65 130
⯠160 360
â¯
80 160
â¯
65 130
⯠900 1800
⯠450 900
⯠360 720
⯠900 1800
⯠450 900
⯠360 720
⯠150 280
â¯
70 120
â¯
50 100
3.5
10
â¯
8.0
20
â¯
12.0 25
â¯
â¯
50 140
â¯
20
60
â¯
15
40
⯠100 200
â¯
40
80
â¯
30
60
â¯
â¯
350
â¯
â¯
150
â¯
â¯
100
No limit
â¯
5
7.5
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
μs
pF
4
2007-10-01
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