TC4015BP_07 Datasheet, PDF (4/9 Pages) Toshiba Semiconductor – Dual 4-Stage Static Shift Register(with serial input/parallel output)

TC4015BP/BF/BFN
Dynamic Electrical Characteristics (Ta = 25°C, V_SS = 0 V, C_L = 50 pF)
Characteristics
Output transition time
(low to high)
Output transition time
(high to low)
Propagation delay time
(CLOCK-Q)
Propagation delay time
(RESET-Q)
Max clock frequency
Min clock pulse width
Min pulse width
(RESET)
Min set-up time
(DATA-CLOCK)
Min hold time
(DATA-CLOCK)
Min removal time
(RESET-CLOCK)
Max clock input rise time
Max clock input fall time
Input capacitance
Symbol
t_TLH
t_THL
t_pLH
t_pHL
t_pHL
f_CL
t_W
t_WH
t_SU
t_H
t_rem
t_rCL
t_fCL
C_IN
Test Condition
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
V_DD (V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Min Typ. Max
⎯
70 200
⎯
35 100
⎯
30
80
⎯
70 200
⎯
35 100
⎯
30
80
⎯ 130 320
⎯
60 160
⎯
50 120
⎯
90 400
⎯
45 200
⎯
40 160
3.0
8
⎯
6.0
17
⎯
8.5
20
⎯
⎯
35 180
⎯
25
80
⎯
20
50
⎯
50 200
⎯
25
80
⎯
20
60
⎯
8
70
⎯
4
40
⎯
0
30
⎯
6
60
⎯
5
30
⎯
4
20
⎯
0
80
⎯
0
30
⎯
0
20
No limit
⎯
5
7.5
Unit
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
μs
pF
4
2007-10-01