TMP89FH42 Datasheet, PDF (39/408 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP89FH42
(5) SLEEP1 mode
In this mode, the high-frequency clock oscillation circuit stops operation, the CPU and the watch-
dog timer stop, and the peripheral circuits operate using the clock that is a quarter of the low-fre-
quency clock (fs).
In the SLEEP1 mode, some peripheral circuits become the same as the states when a reset is
released. For operations of the peripheral circuits in the SLEEP1 mode, refer to the section of each
peripheral circuit.
The SLEEP1 mode can be activated and released in the same way as for the IDLE1 mode. The
operation returns to the SLOW1 mode after this mode is released.
In the SLOW1 or SLEEP1 mode, outputs of the prescaler and stages 1 to 8 of the divider stop.
(6) SLEEP0 mode
In this mode, the high-frequency clock oscillation circuit stops operation, the time base timer oper-
ates using the clock that is a quarter of the low-frequency clock (fs), and the core and the peripheral
circuits stop.
In the SLEEP0 mode, the peripheral circuits stop in the states when the SLEEP0 mode is activated
or become the same as the states when a reset is released. For operations of the peripheral circuits in
the SLEEP0 mode, refer to the section of each peripheral circuit.
The SLEEP0 mode can be activated and released in the same way as for the IDLE0 mode. The
operation returns to the SLOW1 mode after this mode is released.
In the SLEEP0 mode, the CPU stops and the timing generator stops the clock supply to the periph-
eral circuits except the time base timer.
2.3.5.3 STOP mode
In this mode, all the operations in the system, including the oscillation circuits, are stopped and the
internal states in effect before the system was stopped are held with low power consumption.
In the STOP mode, the peripheral circuits stop in the states when the STOP mode is activated or become
the same as the states when a reset is released. For operations of the peripheral circuits in the STOP mode,
refer to the section of each peripheral circuit.
The STOP mode is activated by setting SYSCR1<STOP> to "1".
The STOP mode is released by the STOP mode release signals. After the warm-up time has elapsed, the
operation returns to the mode that was active before the STOP mode, and the operation is restarted by the
instruction that follows the STOP mode activation instruction.
RA001
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