TMP93CS44 Datasheet, PDF (36/224 Pages) Toshiba Semiconductor – CMOS 16-Bit Microcontroller

TMP93CS44/S45
The following (1) to (5) show a flowchart of interrupt processing.
(1) Maskable interrupt
(Main)
EI 1
[1]
INTT0
(Level 1)
(INTT0 interrupt routine)
IFF ← 2
[2]
[3]
[5]
[4]
RETI
IFF ← 1
(2) Non-maskable interrupt
(Main)
D1
[1]
NMI
(Level 7)
(NMI interrupt routine)
IFF ← 7
[2]
[3]
[5]
[4]
RETI
IFF ← 7
During execution of the main program, the CPU
accepts an interrupt request. The CPU increments the
IFF so that the interrupts of level 1 are not accepted
during processing the interrupt routine.
DI instruction is executed in the main program, so that
the interrupts of only level 7 are accepted. The CPU
does not increment the IFF even if the CPU accepts
an interrupt request of level 7.
(3) Interrupt nesting
(4) Software interrupt
(Main)
EI 3
[1]
INTT0
(Level 3)
[9]
(INTT0 interrupt routine) (INTT1 interrupt routine)
IFF ← 4
[3]
IFF ← 5
[2]
[4]
INTT1
(Level 4)
[5]
(Main)
D1
[1]
SWI3
[7]
[8]
RETI
[6]
[5]
IFF ← 3
RETI
IFF ← 4
(SWI3 routine)
[2]
[3]
[4]
RETI
During processing the interrupts of level 3, the IFF is set to 4.
When an interrupt with a level higher than level 4 is generated,
the CPU accepts the interrupt with the higher level, causing
interrupt processing to nest.
The CPU accepts the software interrupt request
during DI status (IFF = 7) because of the level 7.
The IFF is not changed by the software interrupts.
(5) Interrupt sampling timing
(Main)
EI 3
[1]
INTT0
(Level 3)
(INTT0 interrupt routine)
[3]
INTT1
(Level 4)
[2]
XXX
[6]
[5]
[8]
[7]
RETI
[4]
RETI
Example:
(Underline): Instruction
[1], [2], …:
Execution flow
If an interrupt with a level higher than the interrupt being
processed is generated, the CPU accepts the interrupt with the
higher level. The program counter which returns at e is the start
address of INTT0 interrupt routine.
93CS44-34
2004-02-10