TMP92CF26AXBG Datasheet, PDF (353/767 Pages) Toshiba Semiconductor – Original CMOS 32-Bit Microcontroller

TMP92CF26A
Serial Bus Interface Status Register
7
6
5
4
3
2
1
0
SBISR
Bit symbol
(1243H)
Read/Write
Reset State
A read-
Function
modify-write
operation
cannot be
performed
MST
TRX
0
0
Master/ Slave Transmitter/
status
Receiver
monitor
status
0:Slave
monitor
1:Master
0:Receiver
1:Tranmitter
BB
PIN
AL
AAS
AD0
LRB
R
0
1
0
0
0
0
I²C bus status INTSBI
Arbitration Slave
GENERAL Last
monitor
interrupt
lost detection address
CALL
received bit
0:Free
request
monitor
match
detection monitor
1:Busy
monitor
0: −
detection monitor
0: 0
0: Interrupt
requested
1: Interrupt
canceled
1: Detected
monitor
0:Undetected 1: 1
0:Undetected 1: Detected
1: Detected
Last received bit monitor
0 Last received bit was 0
1 Last received bit was 1
GENERAL CALL detection monitor
0 Undetected
1 GENERAL CALL detected
Slave address match detection monitor
0 Slave address don’t match or Undetected
Slave address match or GENERAL CALL
1
detected
Arbitration lost detection monitor
0−
1 Arbitration lost
Note1: Writing in this register functions as SBICR2.
Note2: The initialdata SBISR<PIN> is “1” if SBI operation is enable (SBICR0<SBIEN>=“1”). If SBI operation is disable
(SBICR0<SBIEN>=“0”), the initialdata of SBISR<PIN> is “0”.
Figure 3.15.6 Registers for the I²C bus mode
92CF26A-352
2007-11-21