TB1245N Datasheet, PDF (31/101 Pages) Toshiba Semiconductor – TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC

Deflection correction stage
CHARACTERISTICS
SYMBOL
Vertical Ramp Amplitude
Vertical Amplification
Vertical Amp Maximum Output
Voltage
Vertical Amp Minimum Output Voltage
Vertical Amp Maximum Output
Current
Vertical NF Sawtooth Wave Amplitude
Vertical Amplitude Range
Vertical Linearity Correction Maximum
Value
Vertical S Correction Maximum Value
Vertical NF Center Voltage
Vertical Amplitude EHT Correction
EHT Dynamic Range
E-W NF Maximum DC Value (Picture
Width)
E-W NF Minimum DC Value (Picture
Width)
E-W NF Parabola Maximum Value
(Parabola)
E-W NF Corner Correction (Corner)
Parabola Symmetry Correction
E-W Parabola EHT Value
E-W DC EHT Value
E-W Amp Maximum Output Current
AGC Operating Current 1
AGC Operating Current 2
Vertical Guard Voltage
V Centering DAC Output
V_P49
G_V
V_H53
V_L53
I_MAX1
V_P54
V_PH
V_ℓ
V_S
V_C
V_EHT
V_L
V_H
V_H51
V_L51
V_PB
V_CR
V_TR
V_EH1
V_EH2
I_MAX2
V_AGC0
V_AGC1
V_VG
I₅₄
TEST
CIR-
CUIT
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TB1245N
TEST CONDITIONS
MIN TYP. MAX UNIT
(Note G1) 1.76 1.95 2.15 V_p-p
(Note G2) 20
26
32
dB
(Note G3) 2.5
3
3.5
V
(Note G4) ―
0
0.3
V
(Note G5) 32
45
58
mA
(Note G6) 1.62 1.8 1.98 V_p-p
(Note G7) ±41 ±45 ±49
%
(Note G8) ±10 ±13 ±16
%
(Note G9) ±11 ±16 ±21
%
(Note G10) 4.3
4.5
4.7
V_p-p
(Note G11) 8
9
10
%
1.3
1.8
2.3
(Note G12)
V
5.7
6.2
6.7
(Note G13) 5.5
6.5
7.5
V
(Note G14) 0.55 1.5 2.45
V
(Note G15) 2.2
2.7
3.2
V_p-p
(Note G16) 2
(Note G17) 8
3
4
V_p-p
10
12
%
(Note G18) 2
3.3 4.5
%
(Note G19) 0.6
1
1.4
V
(Note G20) 0.14 0.2 0.28 mA
(Note G21) 160 200 240 µA
(Note G22) 480 600 720 µA
(Note G23) 0.8
1
1.2
V
(Note G24) ―
10
100
nA
31
2001-07-26