TMP86CS44UG Datasheet, PDF (30/172 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

2. Operational Description
2.2 System Clock Controller
TMP86CS44UG
2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode
IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable
interrupts. The following status is maintained during these modes.
1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to
operate.
2. The data memory, CPU registers, program status word and port output latches are all held in the
status in effect before these modes were entered.
3. The program counter holds the address 2 ahead of the instruction which starts these modes.
Starting IDLE1/2 and
SLEEP1/2 modes by
instruction
CPU and WDT are halted
Reset input
Yes
Reset
No
No _{Interrupt request}
Yes
“0”
IMF
Normal
release mode
“1” (Interrupt release mode)
Interrupt processing
Execution of the instruc-
tion which follows the
IDLE1/2 and SLEEP1/2
modes start instruction
Figure 2-10 IDLE1/2 and SLEEP1/2 Modes
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