TC59LM818DMG-33 Datasheet, PDF (30/57 Pages) Toshiba Semiconductor – MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2

SINGLE BANK READ-WRITE TIMING (CL = 6)
TC59LM818DMG-33,-40
CLK
CLK
0
1
2
3
4
5
I_RC = 7 cycles
Command RDA LAL
DESL
6
7
8
9 10 11 12 13 14 15
WRA LAL
I_RC = 7 cycles
DESL
RDA LAL
Address UA LA
UA LA
UA LA
Bank Add. #0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
Hi-Z
DQ
BL = 4
DS
(input)
QS
(output)
Low
Hi-Z
DQ
CL = 6
CL = 6
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
Hi-Z
DQ
CL = 6
BL = 4
DS
(input)
QS
(output)
DQ
Hi-Z
(output)
CL = 6
#0
#0
Q0 Q1
WL = 5
D0 D1
Q0 Q1 Q2 Q3
WL = 5
D0 D1 D2 D3
Q0 Q1
WL = 5
D0 D1
Q0 Q1 Q2 Q3
Read data
WL = 5
D0 D1 D2 D3
Write data
Rev 1.4
2005-10-19 30/57