TA1270BFG Datasheet, PDF (29/39 Pages) Toshiba Semiconductor – PAL / NTSC VIDEO CHROMA AND SYNC PROCESSING SYSTEM FOR PIP / POP / PAP

(Unless otherwise specified, SYNC / SW V_CC = 9 V, DAC / C V_CC = 5 V, preset bus data, Ta = 25°C ± 3°C)
NOTE
CHARACTERISTIC
SW2
SW MODE
SW4 SW5
TP32
TEST CONDITION
TEST METHOD
A
B
A
5V (1) Input signal in the figure below from TG7 to Y2in.
D1 Horizontal Sync Phase
(2) Measure the pin 10 waveform phase difference Sph1 in relation to the
TP8 waveform.
(3) Set the sub address (05) D1 as 1 and measure Sph2 same as (1) above.
Horizontal Blanking Start Phase
D2
Horizontal Blanking Pulse Width
A
B
A
5V (1) Same as (1) for D1.
(2) Measure phase differences HPs and HPw for pin 10 and pin 21,
respectively
Gate Pulse Start Phase
D3
Gate Pulse Width
A
B
A
5V (1) Same as (1) for D1.
(2) Measure the pin 15 waveform phase difference GPs in relation to the pin
10 waveform and measure pulse width GPw.
Horizontal Blanking Pulse Start Phase
A
B
A
5V (1) Same as (1) for D1.
D4
Horizontal Blanking Pulse Width
(2) Measure HPs and HPw same as (2) for D3.
HD Output Start Phase
D5 HD Output Pulse Width
HD Output Amplitude
A
B
A
5V _{(1) Same as (1) for D1.}
(2) Measure the pin 14 waveform phase difference HDs in relation to the pin
10 waveform and measure pulse width HDw and amplitude VHD.
Vertical Blanking Pulse
Start Phase
D6
Vertical Blanking Pulse Width
A
B
A
5V (1) Input 50Hz CVBS signal to Y2in.
(2) Measure the pin 15 waveform phase difference VP50s1 in relation to the
pin 8 waveform and measure pulse width VP50s2.
(3) Input 60Hz CVBS signal to Y2Yin.
(4) Measure VP60s1 and VP60s2 same as (2) above.
D7 Vertical Pulse Width
A
B
A
5V (1) Input 60Hz CVBS signal to Y2in.
(2) Measure the delay Td of the pin 13 vertical pulse in relation to the pin 8
vertical signal and measure the pulse width Tw.
TA1270BFG
29
2005-08-18