TMP86C820UG Datasheet, PDF (28/160 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

2. Operational Description
2.2 System Clock Controller
TMP86C820UG
IDLE1
mode
(a) Single-clock mode
IDLE2
mode
SLEEP2
mode
SLEEP1
mode
(b) Dual-clock mode
IDLE0
mode
Reset release
SYSCR2<TGHALT> = "1"
Note 2
SYSCR2<IDLE> = "1"
Interrupt
NORMAL1
mode
SYSCR1<STOP> = "1"
STOP pin input
SYSCR2<XTEN> = "0"
SYSCR2<XTEN> = "1"
SYSCR2<IDLE> = "1"
Interrupt
NORMAL2
mode
SYSCR1<STOP> = "1"
STOP pin input
SYSCR2<SYSCK> = "0"
SYSCR2<SYSCK> = "1"
SYSCR2<IDLE> = "1"
Interrupt
SLOW2
mode
SYSCR2<XEN> = "1"
SYSCR2<XEN> = "0"
SYSCR2<IDLE> = "1"
Interrupt
SLOW1
mode
SYSCR1<STOP> = "1"
STOP pin input
Note 2
SYSCR2<TGHALT> = "1"
SLEEP0
mode
RESET
STOP
Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1
and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP.
Note 2: The mode is released by falling edge of TBTCR<TBTCK> setting.
Figure 2-6 Operating Mode Transition Diagram
Table 2-1 Operating Mode and Conditions
Operating Mode
RESET
NORMAL1
Single clock IDLE1
IDLE0
STOP
NORMAL2
IDLE2
SLOW2
Dual clock ^SLEEP2
SLOW1
SLEEP1
SLEEP0
STOP
Oscillator
High
Low
Frequency Frequency
Oscillation
Stop
Stop
Oscillation
Oscillation
CPU Core
Reset
Operate
Halt
Operate with
high frequency
Halt
Operate with
low frequency
Halt
Operate with
low frequency
Stop
Halt
Stop
TBT
Reset
Operate
Halt
Operate
Halt
Other
Peripherals
Reset
Operate
Halt
Operate
Halt
Machine Cycle
Time
4/fc [s]
–
4/fc [s]
4/fs [s]
–
Page 16