TMP86FH47BUG Datasheet, PDF (26/218 Pages) Toshiba Semiconductor – 8 Bit Microcontroller TLCS-870/C Series

2. Operational Description
2.2 System Clock Controller
TMP86FH47BUG
The data memory contents become unstable when the power supply is turned on; therefore, the data memo-
ry should be initialized by an initialization routine.
Example :Clears RAM to “00H”. (TMP86FH47BUG)
SRAMCLR:
LD
LD
LD
LD
INC
DEC
JRS
HL, 0040H
A, H
BC, 01FFH
(HL), A
HL
BC
F, SRAMCLR
; Start address setup
; Initial value (00H) setup
2.2 System Clock Controller
The system clock controller consists of a clock generator, a timing generator, and a standby controller.
XIN
XOUT
XTIN
XTOUT
Clock
generator
High-frequency
clock oscillator
Low-frequency
clock oscillator
Timing generator control register
TBTCR
0036H
fc
Timing
Standby controller
generator
0038H
0039H
fs
System clocks
SYSCR1
SYSCR2
System control registers
Clock generator control
Figure 2-2 System Clock Control
2.2.1 Clock Generator
The clock generator generates the basic clock which provides the system clocks supplied to the CPU core
and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for
the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-pow-
er operation based on the low-frequency clock.
The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resona-
tor between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is al-
so possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected.
Page 8