TMP86PM49NG Datasheet, PDF (25/262 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP86PM49NG
2. Operational Description
2.1 CPU Core Functions
The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.
2.1.1 Memory Address Map
The TMP86PM49NG memory is composed OTP, RAM, DBR(Data buffer register) and SFR(Special func-
tion register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86PM49NG memory
address map.
SFR
0000_H
003F_H
0040_H
RAM
043F_H
DBR
0F80_H
0FFF_H
8000_H
64 bytes
1024
bytes
128
bytes
SFR:
RAM:
Special function register includes:
I/O ports
Peripheral control registers
Peripheral status registers
System control registers
Program status word
Random access memory includes:
Data memory
Stack
DBR: Data buffer register includes:
Peripheral control registers
Peripheral status registers
OTP: Program memory
OTP
FFB0_H
FFBF_H
FFC0_H
FFDF_H
FFE0_H
FFFF_H
32768
bytes
Vector table for interrupts
(16 bytes)
Vector table for vector call instructions
(32 bytes)
Vector table for interrupts
(32 bytes)
Figure 2-1 Memory Address Map
2.1.2 Program Memory (OTP)
The TMP86PM49NG has a 32768 bytes (Address 8000H to FFFFH) of program memory (OTP ).
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