TC59LM913AMB-50 Datasheet, PDF (25/46 Pages) Toshiba Semiconductor – MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

MULTIPLE BANK READ TIMING (CL = 4)
TC59LM913AMB-50
CLK
CLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
I_RBD = 2 cycles
I_RBD = 2 cycles I_RBD = 2 cyclesI_RBD = 2 cycles I_RBD = 2 cycles
Command RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL RDA
Address UA LA UA LA
UA LA UA LA UA LA UA LA UA LA UA
Bank Add.
BL = 2
DQS
(output)
DQ
(output)
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
I_RC (Bank"a") = 5 cycles
I_RC (Bank"b") = 5 cycles
Hi-Z
Hi-Z
CL = 4
CL = 4
Qa0Qa1
Qb0Qb1
Bank
"c"
Bank
"d"
Qa0Qa1
Bank
"a"
Qb0 Qb1
Bank
"b"
Qc0Qc1
BL = 4
DQS
Hi-Z
(output)
DQ
Hi-Z
(output)
CL = 4
CL = 4
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2
Note: l_RC to the same bank must be satisfied.
Rev 1.1
2005-08-19 25/46