TMP86FP24 Datasheet, PDF (22/217 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP86FP24
STOP pin
Only when EEPCR<MNPWDW> is “1”.
(The CPU wait period is added.)
V_IH
XOUT pin
NORMAL operation
STOP mode started
by the program.
STOP operation
STOP
Warm up
CPU
wait
NORMAL
operation
STOP operation
STOP mode is released by the hardware at the rising edge
of STOP pin input.
Note: When the STOP mode is started with the EEPCR<MNPWDW> = “1”, the CPU wait for the power supply of flash
control circuit is executed after the STOP warm-up time.
Figure 1.4.9 Edge-sensitive Release Mode
STOP mode is released by the following sequence.
a. In the dual-clock mode, when returning to NORMAL2, both the
high-frequency and low-frequency clock oscillators are turned on; when
returning to SLOW1 mode, only the low-frequency clock oscillator is turned
on. In the single-clock mode, only the high-frequency clock oscillator is
turned on.
b. A STOP warm-up period is inserted to allow oscillation time to stabilize.
During STOP warm up, all internal operations remain halted. Four
different STOP warm-up times can be selected with the SYSCR1<WUT> in
accordance with the resonator characteristics.
c. When the EEPCR<MNPWDW> is “1”, the CPU wait period is inserted to
stabilize the power supply of flash control circuit. During CPU wait, though
CPU operations remain halted, the peripheral function operation is
resumed, and the counting of the timing generator is restarted. After the
CPU wait is finished, normal operation resumes with the instruction
following the STOP mode start instruction.
d. When the EEPCR<MNPWDW> is “0”, normal operation resumes with the
instruction following the STOP mode start instruction after the STOP
warm up.
Note 1: When the STOP mode is released, the start is made after the prescaler and
the divider of the timing generator are cleared to “0”.
Note 2: STOP mode can also be released by inputting low level on the RESET pin,
which immediately performs the normal reset operation.
Note 3: When STOP mode is released with a low hold voltage, the following
cautions must be observed.
The power supply voltage must be at the operating voltage level before
releasing STOP mode. The RESET pin input must also be “H” level, rising
together with the power supply voltage. In this case, if an external time
constant circuit has been connected, the RESET pin input voltage will
increase at a slower pace than the power supply voltage. At this time, there
is a danger that a reset may occur if input voltage level of the RESET pin
drops below the non-inverting high-level input voltage (Hysteresis input).
86FP24-20
2007-08-24