TMP93CS40 Datasheet, PDF (213/248 Pages) Toshiba Semiconductor – CMOS 16-Bit Microcontroller

TMP93CS40/TMP93CS41
4.3 AC Characteristics
(1) VCC = 5 V ± 10%
Variable
16 MHz 20 MHz
No.
Parameter
Symbol
Unit
Min
Max Min Max Min Max
1 Osc. period (= X)
t_OSC
50
31250 62.5
50
ns
2 CLK pulse width
t_CLK
2x − 40
85
60
ns
3 A0 to A23 valid → CLK hold
t_AK
0.5x − 20
11
5
ns
4 CLK valid → A0 to A23 hold
t_KA
1.5x − 70
24
5
ns
5 A0 to A15 valid → ALE fall
t_AL
0.5x − 15
16
10
ns
6 ALE fall → A0 to A15 hold
t_LA
0.5x − 20
11
5
ns
7 ALE high pulse width
t_LL
x − 40
23
10
ns
8 ALE fall → RD / WR fall
t_LC
0.5x − 25
6
0
ns
9 RD / WR rise → ALE rise
t_CL
0.5x − 20
11
5
ns
10 A0 to A15 valid → RD / WR fall
t_ACL
x − 25
38
25
ns
11 A0 to A23 valid → RD / WR fall
t_ACH
1.5x − 50
44
25
ns
12 RD / WR rise → A0 to A23 hold
t_CA
0.5x − 25
6
0
ns
13 A0 to A15 valid → D0 to D15 input
t_ADL
3.0x − 55
133
95 ns
14 A0 to A23 valid → D0 to D15 input
t_ADH
3.5x − 65
154
110 ns
15 RD fall → D0 to D15 input
t_RD
2.0x − 60
65
40 ns
16 RD low pulse width
t_RR
2.0x − 40
85
60
ns
17 RD rise → D0 to D15 hold
t_HR
0
0
0
ns
18 RD rise → A0 to A15 output
t_RAE
x − 15
48
35
ns
19 WR low pulse width
t_WW
2.0x − 40
85
60
ns
20 D0 to D15 valid→ WR rise
t_DW
2.0x − 55
70
45
ns
21 WR rise → D0 to D15 hold
22
A0 to A23 valid → WAIT input
(1 + N) WAIT
mode
23
A0 to A15 valid → WAIT input
(1 + N) WAIT
mode
24 RD / WR fall → WAIT hold
(1 + N) WAIT
mode
t_WD
t_AWH
t_AWL
t_CW
0.5x − 15
2.0x + 0
3.5x − 90
3.0x − 80
16
10
129
108
125
100
ns
85 ns
70 ns
ns
25 A0 to A23 valid → Port input
t_APH
2.5x − 120
36
5 ns
26 A0 to A23 valid → Port hold
t_APH2 ^{2.5x + 50}
206
175
ns
27 WR rise → Port valid
t_CP
200
200
200 ns
28 A0 to A23 valid → RAS fall
t_ASRH ^{1.0x − 40}
23
10
ns
29 A0 to A15 valid → RAS fall
t_ASRL ^{0.5x − 15}
16
10
ns
30 RAS fall → D0 to D15 input
t_RAC
2.5x − 70
86
55 ns
31 RAS fall → A0 to A15 hold
t_RAH
0.5x − 15
16
10
ns
32 RAS low pulse width
t_RAS
2.0x − 40
85
60
ns
33 RAS high pulse width
t_RP
2.0x − 40
85
60
ns
34 CAS fall → RAS rise
t_RSH
1.0x − 40
23
10
ns
35 RAS rise → CAS rise
t_RSC
0.5x − 25
6
0
ns
36 RAS fall → CAS fall
t_RCD
1.0x − 40
23
10
ns
37 CAS fall → D0 to D15 input
t_CAC
1.5x − 65
29
10 ns
38 CAS low pulse width
t_CAS
1.5x − 30
64
40
ns
AC measuring conditions
• Output level: High 2.2 V/Low 0.8 V, CL = 50 pF
(However, CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , R/W , CLK,
RAS , CAS0 to CAS2 )
• Input level: High 2.4 V/Low 0.45 V (AD0 to AD15)
High 0.8 × VCC/Low 0.2 × VCC (except for AD0 to AD15)
93CS40-211
2004-02-10