TMP86P202MG Datasheet, PDF (20/108 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

2. Operational Description
2.2 System Clock Controller
TMP86P202MG
When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back
again. IDLE0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF =
“1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt pro-
cessing is performed. When IDLE0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to NORMAL1 mode.
2.2.3.2 STOP mode
In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The
internal status immediately prior to the halt is held with a lowest power consumption during STOP mode.
STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a
inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After
the warm-up period is completed, the execution resumes with the instruction which follows the STOP
mode start instruction.
IDLE1
mode
IDLE0
mode
Reset release
SYSCR2<TGHALT> = "1"
Note 1
SYSCR2<IDLE> = "1"
Interrupt
NORMAL1
mode
SYSCR1<STOP> = "1"
STOP pin input
Note 1: The mode is released by falling edge of TBTCR<TBTCK> setting.
Figure 2-6 Operating Mode Transition Diagram
RESET
STOP
Table 2-1 Operating Mode and Conditions
Operating Mode
RESET
NORMAL1
Single clock IDLE1
IDLE0
STOP
Oscillator
High
Frequency
Oscillation
Stop
CPU Core
Reset
Operate
Halt
TBT
Reset
Operate
Halt
Other
Peripherals
Reset
Operate
Halt
Machine Cycle
Time
4/fc [s]
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