TC74LVX573F_07 Datasheet, PDF (2/9 Pages) Toshiba Semiconductor – Octal D-Type Latch with 3-State Output

Pin Assignment (top view)
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 V_CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
TC74LVX573F/FT
IEC Logic Symbol
(1)
OE
EN
(11)
LE
C1
(2)
D0
1D
(3)
D1
(4)
D2
(5)
D3
(6)
D4
(7)
D5
(8)
D6
(9)
D7
(19)
Q0
(18)
Q1
(17)
Q2
(16)
Q3
(15)
Q4
(14)
Q5
(13)
Q6
(12)
Q7
Truth Table
Inputs
OE
LE
D
H
X
X
L
L
X
L
H
L
L
H
H
Outputs
Z
Qn
L
H
X: Don’t care
Z: High impedance
Qn: Q outputs are latched at the time when the LE input is taken to a low logic level.
System Diagram
D0
2
D
D1
3
D
D2
4
D
D3
5
D
D4
6
D
D5
7
D
D6
8
D
D7
9
D
11
LE
1
OE
Q
Q
Q
Q
Q
Q
Q
Q
L
L
L
L
L
L
L
L
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
2007-10-17