TMP88PS42FG Datasheet, PDF (187/224 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP88PS42FG
SIOCR1<SIOS> is cleared, the operation will end after all bits of words are transmitted.
That the transmission has ended can be determined from the status of SIOSR<SIOF> because SIOSR<SIOF>
is cleared to “0” when a transfer is completed.
When SIOCR1<SIOINH> is set, the transmission is immediately ended and SIOSR<SIOF> is cleared to
“0”.
When an external clock is used, it is also necessary to clear SIOCR1<SIOS> to “0” before shifting the next
data; If SIOCR1<SIOS> is not cleared before shift out, dummy data will be transmitted and the operation will
end.
If it is necessary to change the number of words, SIOCR1<SIOS> should be cleared to “0”, then
SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to “0”.
SIOCR1<SIOS>
Clear SIOS
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Output)
SO pin
INTSIO interrupt
a₀ a₁ a₂ a₃ a₄ a₅ a₆ a₇ b₀ b₁ b₂ b₃ b₄ b₅ b₆ b₇
DBR
ab
Write Write
(a) (b)
Figure 15-7 Transfer Mode (Example: 8bit, 1word transfer, Internal clock)
SIOCR1<SIOS>
Clear SIOS
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Input)
SO pin
INTSIO interrupt
a₀ a₁ a₂ a₃ a₄ a₅ a₆ a₇ b₀ b₁ b₂ b₃ b₄ b₅ b₆ b₇
DBR
ab
Write Write
(a) (b)
Figure 15-8 Transfer Mode (Example: 8bit, 1word transfer, External clock)
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