TMP86C847SUG Datasheet, PDF (18/160 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

2. Operational Description
2.2 System Clock Controller
TMP86C847SUG
2.2.2 Timing Generator
The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware
from the basic clock (fc or fs). The timing generator provides the following functions.
1. Generation of main system clock
2. Generation of divider output (DVO) pulses
3. Generation of source clocks for time base timer
4. Generation of source clocks for watchdog timer
5. Generation of internal source clocks for timer/counters
6. Generation of warm-up clocks for releasing STOP mode
2.2.2.1 Configuration of timing generator
The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator,
and machine cycle counters.
An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and
TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler
and the divider are cleared to “0”.
SYSCK
DV7CK
High-frequency
clock fc
Low-frequency
clock fs
Main system clock generator
fc or fs
Machine cycle counters
fc/4
12
123456
S
A
Y
B
Multi-
plexer
Divider
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
S Multiplexer
B0
B1
A0 Y0
A1 Y1
Warm-up
controller
Watchdog
timer
Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)
Figure 2-4 Configuration of Timing Generator
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