TA1375FG Datasheet, PDF (17/24 Pages) Toshiba Semiconductor – Single Conversion Tuner for Digital TV / CATV

TA1375FG
Description of PLL Block Operation
- I²C bus control -
The TA1375FG conforms to the I²C-bus format.
The I²C-bus mode enables two-way bus communications with Write Mode, which receives data, and Read Mode, which
sends data.
Write Mode and Rear Mode are set using the last bit (R/W bit) of the address byte. If the last address bit is set to [0],
Write Mode is selected; if it is set to [1], Read Mode is selected.
Address can be set using the hardware bits and four programmable address are available.
With this setting, multiple frequency synthesizers can be used in the same I²C-bus.
The address for the hardware bit setting can be selected by applying voltage to the address setting pin (ADR:pin7).An
address is selected according to the set bits.
If the correct address bytes are received, the serial data (SDA) line is ‘’Low’’ during acknowledgment; when Write Mode
is set, the serial data (SDA) line is ‘’Low’’ during the next acknowledgment if the data byte is programmed.
This IC incorporates a built-in power-on reset circuit for which a detection voltage of approximately 1.4 V has been set.
When the Vcc is supplied, a delay or stoppage in a power supply voltage close to this detection voltage may cause the
power-on reset circuit to malfunction, in which case there is a risk that some data may not be received even after the
recommended voltage has been restored.
A) Write Mode (Setting Command)
When Write Mode is set so that the different types of information may be received, byte1 is used to specify the address
data; byte2 and byte3, the frequency data; byte4, function setting data such as the divider ratio setting; and byte 5, the
output port data (bandswitch data).
Data are latched and transferred at the end of byte 3,byte 4 and byte 5.
Byte 2 and byte 3 are latched and transferred is done with a two bytes set (byte 2 + byte 3).
Once a correct address is received and acknowledged, the data type is determined by whether the first bit of the next byte
is set to [0] or [1]. [0] indicates frequency data, while [1] indicates function setting or output data.
Until the I²C-bus STOP CONDITION is detected, the additional data can be input without transmitting the address data
again. (For example: Frequency sweep is possible with additional frequency data.)
If data transmission is aborted, data programmed before the abort are valid.
[[ BYTE 1 ]]
Hardware bit setting of byte1 is possible using the address data.
The hardware bit is set with the voltage applied to the address-setting pin (ADR:pin7).
[[ BYTE 2 , BYTE 3 ]]
Byte 2 , byte 3 are stored in the 15-bit shift register with counter data for the frequency setting, and control the 15-bit
programmable counter ratio.
The program frequency can be calculated in the following formula :
fosc = frÊ·N
fosc : Program frequency
fr : Phase comparator reference frequency (Step frequency)
N : Counter total divider ratio
fr is calculated using the crystal oscillator and the reference frequency divider ratio set in byte 4 (control byte).
(fr = crystal oscillator frequency / reference divider ratio)
The reference frequency divider ratio can be set to 1/64 , 1/80, 1/24 and 1/28.
When using a 4MHz crystal oscillator, fr=62.5kHz , 50.0kHz , 166.67kHz and 142.86kHz.
The step frequency are 62.5kHz , 50.0kHz , 166.67kHz and 142.86kHz.
[[ BYTE 4 ]]
Byte4 is a control byte used to set the different function. Bit 2 (CP) and controls the output current of the charge-pump
circuit. When bit 2 is set to [0] : the output current is set to +145uA ; when it is set to [1], it is +210uA.
Bit 3 (T2), bit 4 (T1) and bit 5 (T0) are used to set the phase comparator reference signal output and counter divider
output in test mode. (For details of test mode, see the test mode setting table.)
Bit 6 (Rsa) and bit 7 (Rsb) are used to set the crystal reference frequency divider ratio.(For details of the crystal reference
frequency divider ratio, see the table for crystal reference frequency divider ratios.)
Bit 8 (OS) is used to set the charge-pump driver amplifier output setting. When bit 8 is set to [0] the output is ON (the
normal setting used); when it is set to [1] the output is OFF (charge pump is sink mode).
2005/05/23
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