TMP91CW28 Datasheet, PDF (14/286 Pages) Toshiba Semiconductor – Original CMOS 16-Bit Microcontroller

TMP91CW28
3.3 Standby Control and Noise Reduction
The TMP91CW28 incorporates clock gear, standby control and noise reduction circuits to
minimize power consumption as well as noise.
The TMP91CW28 only supports single-clock mode, in which it operates off of the clock
supplied from the X1 and X2 pins.
Figure 3.3.1 shows state transitions in single-clock mode.
IDLE2 mode
Instruction
(Peripherals active) ^Interrupt
IDLE1 mode (Only Instruction
oscillator active)
Interrupt
Reset
(f_OSCH/32)
Reset released
NORMAL mode
(fOSCH/gear value/2)
Instruction
Interrupt
State transitions in single-clock mode
STOP mode
(Whole chip halted)
Figure 3.3.1 State Transitions in Single-clock Mode
f_OSCH: Clock frequency supplied via the X1 and X2 pins
f_FPH: Clock frequency selected by the GEAR[2:0] bit in the SYSCR1
f_SYS: System clock frequency, created by dividing f_FPH by two
1 state: One period of f_SYS
91CW28-12
2006-03-24