TMP86FH12MG Datasheet, PDF (135/228 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

TMP86FH12MG
11.3.5 16-Bit Timer Mode (TC3 and 4)
In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascad-
able to form a 16-bit timer.
When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the
timer is started by setting TC4CR<TC4S> to 1, an INTTC4 interrupt is generated and the up-counter is cleared.
After being cleared, the up-counter continues counting. Program the upper byte and lower byte in this order in
the timer register. (Programming only the upper or lower byte should not be attempted.)
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj, and PPGj pins may output a pulse.
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after programming of TTREGj. Therefore, if TTREGj is changed while the timer is running, an expected
operation may not be obtained.
Note 3: j = 3, 4
Table 11-6 Source Clock for 16-Bit Timer Mode
Source Clock
NORMAL1/2, IDLE1/2 mode
DV7CK = 0
DV7CK = 1
fc/2¹¹
fc/2⁷
fc/2⁵
fc/2³
fs/2³
fc/2⁷
fc/2⁵
fc/2³
SLOW1/2,
SLEEP1/2
mode
fs/2³
–
–
–
Resolution
fc = 16 MHz
fs = 32.768 kHz
128 µs
8 µs
2 µs
500 ns
244.14 µs
–
–
–
Repeated Cycle
fc = 16 MHz
fs = 32.768 kHz
8.39 s
16 s
524.3 ms
–
131.1 ms
–
32.8 ms
–
Example :Setting the timer mode with source clock fc/2⁷ Hz, and generating an interrupt 300 ms later
(fc = 16.0 MHz)
LDW
(TTREG3), 927CH
: Sets the timer register (300 ms÷2⁷/fc = 927CH).
DI
SET
(EIRH). 5
: Enables INTTC4 interrupt.
EI
LD
(TC3CR), 13H
:Sets the operating cock to fc/2⁷, and 16-bit timer mode
(lower byte).
LD
(TC4CR), 04H
: Sets the 16-bit timer mode (upper byte).
LD
(TC4CR), 0CH
: Starts the timer.
TC4CR<TC4S>
Internal
source clock
Counter
0
123
mn-1 mn 0 1 2
mn-1 mn 0 1 2
0
TTREG3
(Lower byte)
?n
TTREG4
(Upper byte)
?
m
INTTC4 interrupt request
Match
detect
Counter
clear
Match
detect
Counter
clear
Figure 11-6 16-Bit Timer Mode Timing Chart (TC3 and TC4)
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