TMP86PM47AUG_07 Datasheet, PDF (124/170 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

10. Synchronous Serial Interface (SIO)
10.3 Function
TMP86PM47AUG
(2) During the transmit/receive operation
When data is written to SIOTDB, SIOSR<TXF> is cleared to “0” and when a data is read from
SIORDB, SIOSR<RXF> is cleared to “0”.
In internal clock operation, in case of the condition described below, the serial clock stops to “H”
level by an automatic-wait function when all of the bit set in the data has been transmitted.
• Next transmit data is not written to SIOTDB after reading a received data from SIORDB.
• Received data is not read from SIORDB after writing a next transmit data to SIOTDB.
• Neither SIOTDB nor SIORDB is accessed after transmission.
The automatic wait function is released by writing the next transmit data to SIOTDB after reading
the received data from SIORDB, or reading the received data from SIORDB after writing the next
data to SIOTDB.
Then, transmit/receive operation is restarted after maximum 1 cycle of serial clock.
In external clock operation, reading the received data from SIORDB and writing the next data to
SIOTDB must be finished before the shift operation of the next data begins.
If the transmit data is not written to SIOTDB after SIOSR<TXF> is set to “1”, transmit error occurs
immediately after shift operation is started. When the transmit error occurred, SIOSR<TXERR> is
set to “1”.
If received data is not read out from SIORDB before next shift operation starts after setting
SIOSR<RXF> to “1”, receive error occurs immediately after shift operation is finished. When the
receive error has occurred, SIOSR<RXERR> is set to “1”.
(3) Stopping the transmit/receive operation
There are two ways for stopping the transmit/receive operation.
• The way of clearing SIOCR1<SIOS>.
When SIOCR1<SIOS> is cleared to “0”, transmit/receive operation is stopped after all trans-
fer of the data is finished. When transmit/receive operation is finished, SIOSR<SIOF> is
cleared to “0” and SO pin is kept in high level.
In external clock operation, SIOCR1<SIOS> must be cleared to “0” before SIOSR<SEF> is
set to “1” by beginning next transfer.
• The way of setting SIOCR1<SIOINH>.
Transmit/receive operation is stopped immediately after SIOCR1<SIOINH> is set to “1”. In
this case, SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are ini-
tialized.
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