TMP86P808DMG Datasheet, PDF (124/160 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

11. Serial Expansion Interface (SEI)
11.3 SEI Operation
TMP86P808DMG
11.3 SEI Operation
During a SEI transfer, data transmission (serial shift-out) and reception (serial shift-in) are performed simulta-
neously. The serial clock synchronizes the timing at which information on the two serial data lines are shifted or
sampled. Slave device can be selected individually using the slave select pin (SS pin). For unselected slave devices,
data on the SEI bus cannot be taken in.
When operating as the master devices, the SS pin can be used to indicate multiple-master bus connection.
11.3.1 Controlling SEI clock polarity and phase
The SEI clock allows its phase and polarity to be selected in software from four combinations available by
using two bits, CPHA and CPOL (SECR<CPHL,CPOL>).
The clock polarity is set by CPOL to select between active-high or active-low (The transfer format is unaf-
fected).
The clock phase is set by CPHA. The master device and the slave devices to communicate with must have
the same clock phase and polarity.
If multiple slave devices with different transfer formats exist on the same bus, the format can be changed to
that of the slave device to which to transfer.
Table 11-2 Clock Phase and Polarity
CPHA
CPOL
SEI control register (SECR 002AH) bit 2
SEI control register (SECR 002AH) bit 3
11.3.2 SEI data and clock timing
The programmable data and clock timing of SEI allows connection to almost all synchronous serial periph-
eral devices. Refer to Section “" 11.5 SEI Transfer Formats "”.
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