TMP86CM46ANG Datasheet, PDF (116/160 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

10. Synchronous Serial Interface (SIO)
10.3 Function
TMP86CM46ANG
(2) During the transmit operation
When data is written to SIOTDB, SIOSR<TXF> is cleared to “0”.
In internal clock operation, in case a next transmit data is not written to SIOTDB, the serial clock
stops to “H” level by an automatic-wait function when all of the bit set in the SIOTDB has been
transmitted. Automatic-wait function is released by writing a transmit data to SIOTDB. Then, trans-
mit operation is restarted after maximum 1-cycle of serial clock.
When the next data is written to the SIOTDB before termination of previous 8-bit data with
SIOSR<TXF> “1”, the next data is continuously transferred after transmission of previous data.
In external clock operation, after SIOSR<TXF> is set to “1”, the transmit data must be written to
SIOTDB before the shift operation of the next data begins.
If the transmit data is not written to SIOTDB, transmit error occurs immediately after shift opera-
tion is started. Then, INTSIO interrupt request is generated after SIOSR<TXERR> is set to “1”.
(3) Stopping the transmit operation
There are two ways for stopping transmits operation.
• The way of clearing SIOCR1<SIOS>.
When SIOCR1<SIOS> is cleared to “0”, transmit operation is stopped after all transfer of the
data is finished. When transmit operation is finished, SIOSR<SIOF> is cleared to “0” and
SO pin is kept in high level.
In external clock operation, SIOCR1<SIOS> must be cleared to “0” before SIOSR<SEF> is
set to “1” by beginning next transfer.
• The way of setting SIOCR1<SIOINH>.
Transmit operation is stopped immediately after SIOCR1<SIOINH> is set to “1”. In this
case, SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are initial-
ized.
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin outout
SO pin
SIOSR<TXF>
INTSIO
interrupt
request
SIOTDB
Clearing SIOS
Start shift
operation
Start shift
operation
Start shift
operation
Automatic wait
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
C7 C6 C5 C4 C3 C2 C1 C0
A
B
C
Writing transmit Writing transmit
data A
data B
Writing transmit
data C
Figure 10-6 Example of Internal Clock and MSB Transmit Mode
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