TMP91CP27 Datasheet, PDF (115/246 Pages) Toshiba Semiconductor – Original CMOS 16-Bit Microcontroller

TMP91CP27
(3) Timer registers (TB0RG0H/L and TB0RG1H/L)
These two 16-bit registers are used to set the interval time. When the value in the up
counter UC0 matches set value of timer register, the comparator match detect signal
will be active.
Setting data for both upper and lower timer registers are always needed. For
example, either using 2-byte data transfer instruction or using 1-byte date transfer
instruction twice for lower 8 bits and upper 8 bits in order.
The TB0RG0 timer register has a double-buffer structure, which is paired with
register buffer 0. The timer control register TB0RUN<TB0RDE> control whether the
double buffer structure should be enabled or disabled: it is disabled when <TB0RDE> =
0, and enabled when <TB0RDE> = 1.
When the double buffer is enabled, data is transferred from the register buffer to the
timer register when the values in the up counter (UC0) and the timer register TB0RG1
match.
After a Reset, TB0RG0 and TB0RG1 are undefined. To use the 16-bit timer after
reset, data should be written beforehand.
When reset, <TB0RDE> is initialized to 0, whereby the double buffer is disabled. To
use the double buffer, write data to the timer register, set <TB0RDE> to 1, then write
following data to the register buffer.
TB0RG0 and the register buffer are allocated to the same memory address
0188H/0189H. When <TB0RDE> = 0, same value will be written to both the timer
register and register buffer. When <TB0RDE> = 1, the value is written into only the
register buffer.
Therefore, when write initial value to timer register, set register buffer to disable.
The addresses of the timer registers are as follows:
TMRB0
TB0RG0
Upper 8-bit
(TB0RG0H)
Lower 8-bit
(TB0RG0L)
000189H
000188H
TB0RG1
Upper 8-bit
(TB0RG1H)
Lower 8-bit
(TB0RG1L)
00018BH
00018AH
The TB0RG0 to TB0RG1 are write-only registers and thus cannot be read.
91CP27-113
2003-11-05