TMP91C824_05 Datasheet, PDF (112/260 Pages) Toshiba Semiconductor – Original CMOS 16-Bit Microcontroller

TMP91C824
In this mode, the value of the register buffer will be shifted into TA0REG if 2ⁿ
overflow is detected when the TA0REG double buffer is enabled.
Use of the double buffer facilitates the handling of low duty ratio waves.
Match with TA0REG
2ⁿ overflow
TA0REG
(Value to be compared)
Register buffer
Up counter = Q₁
Q₁
Q₂
Up counter = Q₂
Shift into TA0REG
Q₂
Q₃
TA0REG (Register buffer)
write
Figure 3.7.18 Register Buffer Operation
Example: To output the following PWM waves on the TA1OUT pin at fc = 33MHz:
17.9 μs
31.0 μs
* Clock state
System clock: High frequency (fc)
Clock gear: 1 (fc)
Prescaler clock: f_FPH
To achieve a 31.0 μs PWM cycle by setting φT1 = (2³/fc)s (at fc = 33 MHz):
31.0 μs ÷ (2³/fc)s ≈ 128 = 2ⁿ
Therefore n should be set to 7.
Since the low-level period is 37.0 μs when φT1 = (2³/fc)s,
set the following value for TA0REG:
17.9 μs ÷ (2³/fc)s ≈ 74 = 4AH
TA01RUN
TA01MOD
MSB
LSB
76543210
←– X X X – – – 0
←1 1 1 0 – – 0 1
TA0REG
TA1FFCR
←0 1 0 0 1 0 1 0
←X X X X 1 0 1 X
PBCR
←X – – – – – 1 –
PBFC
←X – – – – – 1 X
TA01RUN ← 1 X X X – 1 – 1
X: Don’t care, −: No change
Stop TMRA0 and clear it to 0.
Select 8-bit PWM mode (Cycle: 2⁷) and select φT1 as the
input clock.
Write 4AH.
Clear TA1FF to 0, enable the inversion and double buffer.
Set PB1 and the TA1OUT pin.
Start TMRA0 counting.
91C824-110
2005-12-16