TCD2704D Datasheet, PDF (11/16 Pages) Toshiba Semiconductor – High sensitive and low dark current 7500 elements x 4 line

Timing Requirements (cont.)
Characteristics
Symbol
Min
Pulse timing of SH and φ1
SH pulse rise time, fall time
SH pulse width
Pulse timing of SH and CP
Pulse timing of SH and CP
(line clamp mode)
Pulse timing of SH and SW
φ1, φ2 pulse rise time, fall time
RS pulse rise time, fall time
RS pulse width
Pulse timing of RS and CP
Pulse timing of φ_1A, φ_2A and CP
CP pulse rise time, fall time
CP pulse width
(Note 13)
Reference level settle time
(bit clamp mode)
Video data delay time
(Note 14)
Reference level settle time
(line clamp mode)
t1
t5
t2, t4
t3
t6
t7
t8
t9, t10
t11, t12
t13
t14
t15
t16, t17
t18
t19
t20
t21
120
800
0
3000
200
10
100
0
0
10 (20)
0
0
0
30 (3000)



Note 12: Typ. is the case of f_RS = 1.0 MHz.
Note 13: Line clamp Mode inside ( ).
Note 14: Load Resistance is 100 kΩ.
Note 15: Typical settle time to about 1% of final value.
Note 16: Typical settle time to about 1% of the peak.
Typ.
(Note 12)
Max
Unit
1000
1000

ns

50

ns
5000

ns
500

ns
100

ns
500
t3 − 100
ns
50

ns
20

ns
80

ns
40

ns
20

ns
20

ns
80 (5000)

ns
20
40 (Note 16) ns
20
40 (Note 15) ns
30
50 (Note 16) ns
Clamp Mode
Clamp Means
Bit clamp
Line clamp
CP Input Pulse
CP Pulse
“H” or SH
Changeover Switch Mode
Output Type
Color
B/W
SW1 Input Pulse
“H”
“L”
SW2 Input Pulse
“L”
“H”
TCD2704D
11
2001-04-13