TA1384FNG Datasheet, PDF (11/22 Pages) Toshiba Semiconductor – Mixer/Oscillator and PLL IC for TV/VCR Tuner

TA1384FNG
Description of PLL Block Operation
- I²C bus control -
The TA1384FNG conforms to the I²C-bus format.
I²C-bus mode enables two-way bus communications with Write Mode, which receives data, and Read Mode, which sends
data.
Write Mode and Read Mode are set using the last bit (R/W bit) of the address byte. If the last address bit is set to [0],
Write Mode is selected; if it is set to [1], Read Mode is selected.
Addresses can be set using the hardware bits, and four programmable addresses are available. With this setting,
multiple frequency synthesizers can be used in the same I²C-bus. The address for the hardware bit setting can be selected
by applying voltage to the address setting pin (ADR: pin 3).An address is selected according to the set bits.
If the correct address bytes are received, the serial data (SDA) line is “Low” during acknowledgment; when Write Mode
is set, the serial data (SDA) line is “Low” during the next acknowledgment if the data byte is programmed. The IC is
equipped with 1/2 and 1/4 built-in prescalers, and it is possible to change from one prescaler to the other using input data.
When a frequency step of 62.5 kHz is selected, the 1/2 prescaler operates with a divider ratio of 1024 to 4095, and the 1/4
prescaler operates with a divider ratio of 4096 to 32767.
When the frequency step selected is 31.25 kHz and 50 kHz, the 1/2 prescaler operates with a divider ratio of 1024 to 8191,
and the 1/4 prescaler operates with a divider ratio of 8192 to 32767.
In addition, even if the prescaler is changed, the data is calculated in the internal circuit and is processed so that the
comparison frequency in each the frequency step does not change.
For a frequency step of 62.5 kHz: 15.625 kHz comparison frequency
For a frequency step of 50 kHz: 12.5 kHz comparison frequency
For a frequency step of 31.25 kHz: 7.8125 kHz comparison frequency
This IC incorporates a built-in power-on reset circuit for which a detection voltage of approximately 1.4 V has been set.
When the Vcc is supplied, a delay or stoppage in a power supply voltage close to this detection voltage may cause the
power-on reset circuit to malfunction, in which case there is a risk that some data may not be received even after the
recommended voltage has been restored.
A) Write Mode (Setting Command)
When WRITE mode is set so that the different types of information may be received, byte 1 is used to specify the address
data; byte 2 and byte 3, the frequency data; byte 4, function setting data such as the divider ratio setting; and byte 5, the
output port data (bandswitch data).
Data are latched and transferred one after the other in the case of byte 3, byte 4 and byte 5, while byte 2 and byte 3 are
latched and transferred as a two-byte set (byte 2 + byte 3).
Once a correct address is received and acknowledged, the data type is determined by whether the first bit of the next
byte is set to [0] or [1]. [0] indicates frequency data, while [1] indicates function setting or output data.
Until the I²C-bus STOP CONDITION is detected, the additional data can be input without transmitting the address
data again. (For example: Frequency sweep is possible with additional frequency data.)
If data transmission is aborted, data programmed before the abort are valid.
BYTE 1
Hardware bit setting of byte 1 is possible using the address data.
The hardware bit is set with the voltage applied to the address-setting pin (ADR: pin 3).
BYTE 2, BYTE 3
Byte 2 , byte 3 are stored in the 15-bit shift register with counter data for the frequency setting, and control the 15-bit
programmable counter ratio.
The program frequency can be calculated in the following formula:
fosc = 4 x fr x N.
fosc : Program frequency
4
: Prescaler
fr
: Phase comparator reference frequency (step frequency)
N
: Counter total divider ratio
fr is calculated using the crystal oscillator and the reference frequency divider ratio set in byte 4 (control byte): fr = crystal
oscillator frequency / reference divider ratio.
The reference frequency divider ratio can be set to 1/512, 1/320, and 1/256.
When using a 4-MHz crystal oscillator, fr = 7.8125 kHz, 12.5 kHz, and 15.625 kHz.
The step frequency is 31.25 kHz, 50.0 kHz, and 62.5 kHz.
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2004/11/24