TC94A14F Datasheet, PDF (10/17 Pages) Toshiba Semiconductor – Digital Servo Single-Chip Processor for Use in CD Player

TC94A14F/FA/FB
3. DATA, CLCK Input/Output Timing
(1) CLCK input mode (regardless of setting of HS and UHS bits of SPEED command)
Characteristics
Symbol
Test
Circuit
Test Condition
Min Typ. Max Unit
Clock pulse width
“H” level
“L” level
tHW
¾
CLCK input mode
tLW
¾
50
¾
¾
50
¾
¾
Input setup time
tSU
¾ CLCK input mode
¾
¾
¾
Transfer time (1)
Transfer time (2)
“L” level
“H” level
“L” level
“H” level
“L” level
tpHL1
tpLH₅2
tpHL₅2
tpLH₅2
tpHL₅2
¾ CLCK input mode
¾
CLCK input mode
¾
¾
V_DD5 = 3.3 V
¾
¾
¾
5
ns
¾
¾
15
¾
¾
15
¾
¾
20
¾
¾
20
SFSY
CLCK
tpHL1
tSU
tpHL₅2, tpLH₅2
tpHL₃2, tpLH₃2
tHW
tLW
DATA
SUBP
SUBQ
(2) CLCK output mode (tHW, tLW, tpLH3 only, ´ 1/n at ´n speed)
Characteristics
Symbol
Test
Circuit
Test Condition
Clock pulse width
“H” level
“L” level
tHW
¾
CLCK output mode
tLW
¾
Transfer time (1)
“L” level
tpHL1
¾ CLCK output mode
Transfer time (2)
Transfer time (3)
“H” level
“L” level
“H” level
“L” level
“H” level
tpLH₅2
tpHL₅2
tpLH₃2
tpHL₃2
tpLH3
¾
CLCK output mode
¾
¾
V_DD5 = 3.3 V
¾
¾ CLCK output mode
SFSY
CLCK
tpHL1
tpLH3
tpHL₅2, tpLH₅2
tpHL₃2, tpLH₃2
tHW
tLW
Min Typ. Max Unit
¾
¾ 950
¾
¾ 950
¾
¾
5
¾
¾
15
ns
¾
¾
15
¾
¾
20
¾
¾
20
¾
¾ 850
DATA
SUBP
SUBQ
10
2002-11-18