TPC6901A Datasheet, PDF (1/7 Pages) Toshiba Semiconductor – Multi-Chip Transistor Silicon NPN / PNP Epitaxial Type

TPC6901A
TOSHIBA Multi-Chip Transistor Silicon NPN / PNP Epitaxial Type
TPC6901A
High-Speed Switching Applications
MOS Gate Drive Applications
Unit: mm
• NPN and PNP transistors are mounted on a compact and slim package.
• High DC current gain : NPN h_FE = 400 to 1000
: PNP h_FE = 200 to 500
• Low collector-emitter saturation voltage
: NPN V_{CE (sat)} = 0.17 V (max)
: PNP V_{CE (sat)} = －0.23 V (max)
• High-speed switching : NPN t_f = 85 ns (typ.)
: PNP t_f = 70 ns (typ.)
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Collector-base voltage
Collector-emitter voltage
Collector-emitter voltage
Emitter-base voltage
Collector current
DC (Note 1)
Pulse (Note 1)
Base current
Collector power
Single-device
dissipation (t=10 s) operation
Collector power
dissipation (DC)
Single-device
operation
Single-device value
at dual operation
Thermal resistance,
junction to ambient
(t=10 s)
Single-device
operation
Thermal resistance,
junction to ambient
(DC)
Single-device
operation
Single-device value
at dual operation
Junction temperature
Storage temperature range
V_CBO
V_CEX
V_CEO
V_EBO
I_C
I_CP
I_B
P_C
(Note 2)
P_C
(Note 2)
P_C
(Note 2)
R_{th (j-a)}
(Note 2)
R_{th (j-a)}
(Note 2)
R_{th (j-a)}
(Note 2)
T_j
T_stg
Rating
Unit
NPN PNP
100 −50
V
80 −50
V
50 −50
V
7
−7
V
1.0 −0.7
A
5.0 −5.0
A
0.1 −0.1
A
500
mW
400
mW
330
250
°C/W
312
378
150
−55 to 150
°C/W
°C
°C
JEDEC
―
JEITA
―
TOSHIBA
2-3T1A
Weight: 0.011 g (typ.)
Note 1: Please use devices on condition that the junction temperature is below 150℃.
Note 2: Mounted on FR4 board (glass epoxy, 1.6 mm thick, Cu area: 645 mm²)
Note 3: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
1
2009-07-06