TK50X15J1 Datasheet, PDF (1/6 Pages) Toshiba Semiconductor – Field Effect Transistor Silicon N Channel MOS Type (Ultra-High-Speed U-MOSⅢ)

TK50X15J1
TOSHIBA Field Effect Transistor Silicon N Channel MOS Type (Ultra-High-Speed U-MOSⅢ)
TK50X15J1
DC-DC Converters
• Low drain-source ON-resistance: R_{DS (ON)} = 22 mΩ (typ.)
• High forward transfer admittance: |Y_fs| = 90 S (typ.)
• Low leakage current: I_DSS = 10 μA (max) (V_DS = 150 V)
• Enhancement mode: V_th = 2.0 to 4.0 V (V_DS = 10 V, I_D = 1 mA)
Unit: mm
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Drain-source voltage
Drain-gate voltage (R_GS = 20 kΩ)
Gate-source voltage
Drain current
DC (Note 1)
Pulse (Note 1)
Drain power dissipation (Tc = 25°C)
Single pulse avalanche energy
(Note 2)
Avalanche current
Repetitive avalanche energy (Note 3)
Channel temperature
(Note 4)
Storage temperature range (Note 4)
V_DSS
V_DGR
V_GSS
I_D
I_DP
P_D
E_AS
I_AR
E_AR
T_ch
T_stg
150
V
150
V
±20
V
50
A
150
125
W
182
mJ
50
A
10.9
mJ
175
°C
−55 to 175
°C
JEDEC
―
JEITA
SC-97
TOSHIBA
2-9F1B
Weight: 0.74 g (typ.)
Note: Using continuously under heavy loads (e.g. the application of high
temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the
absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability
Handbook (“Handling Precautions”/’’Derating Concept and Methods’’) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
Thermal Characteristics
Characteristics
Symbol
Max
Unit
Thermal resistance, channel to case
R_{th (ch-c)}
1.2
°C/W
Note 1: Ensure that the channel temperature does not exceed 175℃.
Note 2: V_DD = 50V, T_ch = 25°C (initial), L = 110 μH, R_G = 25 Ω, I_AR = 50A
Note 3: Repetitive rating: pulse width limited by maximum channel
temperature
Note 4: The definitions of the absolute maximum channel and storage
temperatures are base on AEC-Q101.
This transistor is an electrostatic-sensitive device. Handle with care.
Circuit Configuration
Note: Use the S1 pin to return the
gate signal to source. Board traces
should be designed so the main
current flows to the S2 pin.
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2009-09-29