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THGBM5G7A2JBAIM Datasheet, PDF (1/1 Pages) Toshiba Semiconductor – Semiconductor & Storage Products Company
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Home. tvlemorv. NAND Flash. tv1LC NAND. e•tv1f111C't.t
e•MMC™
The interface of eoMMCno is compliant with Version 4.4/4.41 of the JEDEC eoMMCno standard for high-speed memory cards. Users can easily use eoMMCno in various products as
an embedded MMC memory device (eoMMcno compliant). Since eoMMcno integrates a NAND nash memory and a controller chip in a single package, it can perform such controls as
error corrections, wear leveling and bad-block management internally. All eoMMCno parts have compatible pin-layouts for all derivatives and generations. This frees users from the
worry of control operations otherwise required for NAND nash memory, making it easy to use.
Product List of eoMMcno
Capacity Part Number
Power Supply
I e-MMC
Version
Speed
(MHz)
~ ~c i-~~:c..Q.
.:
..
,
-
-
--
-
--
-
I Operating
(·c)
Temperature
Package
2 GByte jTHGBM4G401 HBAIR 4.41 to 52
1.65 to 1.95, 2.7 to 3.62
4 GByte THGBM5G5A1JBAIR" 4.41 a to 200
1.70 to 1.95, 2.7 to 3.6
8 GByte jTHGBM5G6A2JBAIR" 4.41 a to 200
1.70 to 1.95, 2.7 to 3.6
16 GByte THGBM5G7A2JBAtM• 4.41 a to 200 2.7 to 3.6
-25 to 85
1-::-:--,-.:_-1].,--.,...,---,-,...,----,,---}---f--::-:-l
1.70 to 1.95, 2.7 to 3.6
32 Gbyte THGBM5G8A4JBAtM• 4.41 a to 200
64 Gbyte THGBM5G9B8JBAtE• 4.41 a to 200
1.70 to 1.95, 2.7 to 3.6
128 Gbyte THGBM4TODBGBAIJ 4.41 to 52
1.65 to 1.95, 2.7 to 3.6
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P-VFBGA153-1113-0.50-002
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~
I I CPU
Bad Block
Higl>-added
Management & value with integrated
Wear leveling
j ECC j
I I NAND IIF
controller chip
in paci<age
less susceptible
to the impact of
.•••••••••.•••••••••••, specification changes
i MLC NAND :
! Driver !
arising from
changes In
·----------------------' NAND generations
MLC NAND Chip
Solid line: Hardware
Dotted line: Software
~MMCT"'
CPU :
I HS-MMC 1/ F
..................... ,
.. H8-MMC !
Driver
"!..
HS-MMC 1/F
Bad Block
Management &
Wear leveling
ECC
-NA.N...D..IIF
MLC NAND Chip I
.-MMC' " Is the trademark of JEDECIMMCA.
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