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TC7W241FUTE12LF Datasheet, PDF (1/6 Pages) Toshiba Semiconductor – TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC7W241FU
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC7W241FU
Non-Inverted, 3-State Outputs
The TC7W241FU is a high speed C2MOS Dual Bus Buffers
fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the C2MOS low power dissipation.
It is a non-inverting 3-state buffer has one active-high and one
active-low output enable.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: tpd = 10 ns (typ.) at VCC = 5 V
• Low power dissipation: ICC = 2 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Output drive capability: 15 LSTTL loads
• Symmetrical output impedance: |IOH| = IOL = 6 mA (min)
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2 to 6 V
Weight: 0.02 g (typ.)
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC VCC/ground current
Power dissipation
Storage temperature range
Lead temperature (10 s)
VCC
VIN
VOUT
IIK
IOK
IOUT
ICC
PD
Tstg
TL
−0.5 to 7
V
−0.5 to VCC + 0.5
V
−0.5 to VCC + 0.5
V
±20
mA
±20
mA
±35
mA
±37.5
mA
300
mW
−65 to 150
°C
260
°C
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if
the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
1
2009-09-30