TC7MH175FK Datasheet, PDF (1/7 Pages) Toshiba Semiconductor – TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC7MH175FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC7MH175FK
Quad D-Type Flip-Flop with Clear
The TC7MH175FK is an advanced high speed CMOS quad
D-type flip-flop fabricated with silicon gate C²MOS technology.
It achieves the high speed operation similar to equivalent
bipolar schottky TTL while maintaining the CMOS low power
dissipation.
These four flip-flops are controlled by a clock input (CK) and a
clear input (CLR).
The information data applied to the D inputs (D1 thru D4) are
transferred to the outputs (Q1 thru Q4 and Q1 thru Q4) on the
positive-going edge of the clock pulse.
When the CLR input is held low , the Q outputs are at the low
logic level and the Q outputs are at the high logic level,
regardless of other input conditions.
Weight: 0.02 g (typ.)
An input protection circuit ensures that 0 to 7 V can be applied
to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and
two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and
input voltages.
Features
• High speed: fmax = 210 MHz (typ.) (VCC = 5 V)
• Low power dissipation: ICC = 4 µA (max) (Ta = 25°C)
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Power down protection is provided on all inputs.
• Balanced propagation delays: tpLH ≈ tpHL
• Wide operating voltage range: VCC (opr) = 2~5.5 V
• Low noise: VOLP = 0.8 V (max)
• Pin and function compatible with 74ALS175
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2001-10-23