TC7MET573AFK_07 Datasheet, PDF (1/7 Pages) Toshiba Semiconductor – Octal D-Type Latch with 3-State Output

TC7MET573AFK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC7MET573AFK
Octal D-Type Latch with 3-State Output
The TC7MET573AFK is an advanced high speed CMOS octal
latch with 3-state output fabricated with silicon gate C²MOS
technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This 8-bit D-type latch is controlled by a latch enable input
(LE) and a output enable input (OE).
When the OE input is high, the eight outputs are in a high
impedance state.
The input voltage are compatible with TTL output voltage.
This device may be used as a level converter for interfacing 3.3
V to 5 V system.
Weight: 0.03 g (typ.)
Input protection and output circuit ensure that 0 to 5.5 V can
be applied to the input and output ^(Note) pins without regard to the supply voltage. These structure prevents device
destruction due to mismatched supply and input/output voltages such as battery back up, hot board insertion, etc.
Note: V_CC = 0 V
Features
• High speed: t_pd = 7.7 ns (typ.) (V_CC = 5 V)
• Low power dissipation: I_CC = 4 μA (max) (Ta = 25°C)
• Compatible with TTL outputs: V_IL = 0.8 V (max)
V_IH = 2.0 V (min)
• Power down protection is provided on all inputs and outputs.
• Balanced propagation delays: t_pLH ≈ t_pHL
• Low noise: V_OLP = 1.5 V (max)
• Pin and function compatible with the 74 series (74AC/HC/F/ALS/LS etc.) 573 type.
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2007-10-19