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TC7MA2373FK_07 Datasheet, PDF (1/11 Pages) Toshiba Semiconductor – Low-Voltage Octal D-Type Latch with 3.6 V Tolerant Inputs and Outputs | |||
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TC7MA2373FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC7MA2373FK
Low-Voltage Octal D-Type Latch with 3.6 V Tolerant Inputs and Outputs
The TC7MA2373FK is a high performance CMOS octal D-type
latch. Designed for use in 1.8 V, 2.5 V or 3.3 V systems, it
achieves high speed operation while maintaining the CMOS low
power dissipation.
It is also designed with over voltage tolerant inputs and
outputs up to 3.6 V.
This 8 bit D-type latch is controlled by a latch enable input
(LE) and output enable input (OE).
When the OE input is high, the eight outputs are in a high
impedance state.
The 26 ⦠series resistor helps reducing output overshoot and
Weight: 0.03 g (typ.)
undershoot without external resistor.
All inputs are equipped with protection circuits against static discharge.
Features
⢠26 ⦠series resistors on outputs.
⢠Low voltage operation: VCC = 1.8~3.6 V
⢠High speed operation: tpd = 5.1 ns (max) (VCC = 3.0~3.6 V)
tpd = 6.1 ns (max) (VCC = 2.3~2.7 V)
tpd = 9.8 ns (max) (VCC = 1.8 V)
⢠3.6 V tolerant inputs and outputs.
⢠Output current: IOH/IOL = ±12 mA (min) (VCC = 3.0 V)
IOH/IOL = ±8 mA (min) (VCC = 2.3 V)
IOH/IOL = ±4 mA (min) (VCC = 1.8 V)
⢠Latch-up performance: â300 mA
⢠ESD performance: Machine model ⥠±200 V
Human body model ⥠±2000 V
⢠Package: VSSOP (US)
⢠Power down protection is provided on all inputs and outputs.
⢠Supports live insertion/withdrawal (*)
*: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
1
2007-10-19
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